Datasheet

196
32142D–06/2013
ATUC64/128/256L3/4U
11.6 Module Configuration
The specific configuration for each HMATRIX instance is listed in the following tables.The mod-
ule bus clocks listed here are connected to the system bus clocks. Please refer to the Power
Manager chapter for details.
11.6.1 Bus Matrix Connections
The bus matrix has the several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG3 is
associated with the Internal SRAM Slave Interface.
Accesses to unused areas returns an error result to the master requesting such an access.
Table 11-3. HMATRIX Clocks
Clock Name Description
CLK_HMATRIX Clock for the HMATRIX bus interface
Table 11-4. High Speed Bus Masters
Master 0 CPU Data
Master 1 CPU Instruction
Master 2 CPU SAB
Master 3 SAU
Master 4 PDCA
Master 5 USBC
Table 11-5. High Speed Bus Slaves
Slave 0 Internal Flash
Slave 1 HSB-PB Bridge A
Slave 2 HSB-PB Bridge B
Slave 3 Internal SRAM
Slave 4 SAU