Datasheet

168
32142D–06/2013
ATUC64/128/256L3/4U
10.6 User Interface
The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base
address.
Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
The following addresses are used by SAU channel registers. All offsets are relative to the SAU’s HSB base address. The
number of channels implemented is device specific, refer to the Module Configuration section at the end of this chapter.
Table 10-1. SAU Configuration Register Memory Map
Offset Register Register Name Access Reset
0x00 Control Register CR Write-only 0x00000000
0x04 Configuration Register CONFIG Write-only 0x00000000
0x08 Channel Enable Register High CERH Read/Write 0x00000000
0x0C Channel Enable Register Low CERL Read/Write 0x00000000
0x10 Status Register SR Read-only 0x00000400
0x14 Interrupt Enable Register IER Write-only 0x00000000
0x18 Interrupt Disable Register IDR Write-only 0x00000000
0x1C Interrupt Mask Register IMR Read-only 0x00000000
0x20 Interrupt Clear Register ICR Write-only 0x00000000
0x24 Parameter Register PARAMETER Read-only -
(1)
0x28 Version Register VERSION Read-only -
(1)
Table 10-2. SAU Channel Register Memory Map
Offset Register Register Name Access Reset
0x00 Remap Target Register 0 RTR0 Read/Write N/A
0x04 Remap Target Register 1 RTR1 Read/Write N/A
0x08 Remap Target Register 2 RTR2 Read/Write N/A
... ... ... ... ...
0x04*n Remap Target Register n RTRn Read/Write N/A
0xFC Unlock Register UR Write-only N/A