Datasheet

16
32142D–06/2013
ATUC64/128/256L3/4U
IMCK I2S Master Clock Output
ISCK I2S Serial Clock I/O
ISDI I2S Serial Data In Input
ISDO I2S Serial Data Out Output
IWS I2S Word Select I/O
JTAG module - JTAG
TCK Test Clock Input
TDI Test Data In Input
TDO Test Data Out Output
TMS Test Mode Select Input
Power Manager - PM
RESET_N Reset Input Low
Pulse Width Modulation Controller - PWMA
PWMA35 - PWMA0 PWMA channel waveforms Output
PWMAOD35 -
PWMAOD0
PWMA channel waveforms, open drain
mode
Output
Not all channels support open
drain mode
System Control Interface - SCIF
GCLK9 - GCLK0 Generic Clock Output Output
GCLK_IN2 - GCLK_IN0 Generic Clock Input Input
RC32OUT RC32K output at startup Output
XIN0 Crystal 0 Input
Analog/
Digital
XIN32 Crystal 32 Input (primary location)
Analog/
Digital
XIN32_2 Crystal 32 Input (secondary location)
Analog/
Digital
XOUT0 Crystal 0 Output Analog
XOUT32 Crystal 32 Output (primary location) Analog
XOUT32_2 Crystal 32 Output (secondary location) Analog
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
NPCS3 - NPCS0 SPI Peripheral Chip Select I/O Low
SCK Clock I/O
Timer/Counter - TC0, TC1
A0 Channel 0 Line A I/O
A1 Channel 1 Line A I/O
A2 Channel 2 Line A I/O
Table 3-7. Signal Descriptions List