Features • High-performance, Low-power 32-bit Atmel® AVR® Microcontroller • • • • • • • • • • • • • • • – Compact Single-cycle RISC Instruction Set Including DSP Instructions – Read-modify-write Instructions and Atomic Bit Manipulation – Performance • Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State) • Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State) – Memory Protection Unit (MPU) • Secure Access Unit (SAU) providing User-defined Peripheral Protection picoPower® Technology f
ATUC64/128/256L3/4U • One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals – Up to 15 SPI Slaves can be Addressed • Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible • One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution – Internal Temperature Sensor • Eight Analog Comparators (AC) with Optional Window Detection • Capacitive Touch (CAT) Module • • • • • • • – Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch A
ATUC64/128/256L3/4U 1. Description The Atmel® AVR® ATUC64/128/256L3/4U is a complete system-on-chip microcontroller based on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a highperformance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance.
ATUC64/128/256L3/4U The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it to a known reference clock. The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same time, thanks to the rich end-point configuration. The device includes six identical 16-bit Timer/Counter (TC) channels.
ATUC64/128/256L3/4U 2. Overview Block Diagram Figure 2-1. Block Diagram EVTO_N TCK TDO TDI TMS DATAOUT JTAG INTERFACE DATA INTERFACE M M S AVR32UC CPU NEXUS CLASS 2+ OCD aWire RESET_N INSTR INTERFACE MEMORY INTERFACE MCKO MDO[5..0] MSEO[1..
ATUC64/128/256L3/4U 2.2 Configuration Summary Table 2-1.
ATUC64/128/256L3/4U 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section . ATUC64/128/256L4U TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-1.
ATUC64/128/256L3/4U ATUC64/128/256L4U TLLGA48 Pinout 37 36 35 34 33 32 31 30 29 28 27 26 25 PA15 PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB09 PA04 PA11 PA13 PA20 Figure 3-2.
ATUC64/128/256L3/4U PA14 VDDANA ADVREFP GNDANA PB08 PB07 PB06 PB22 PB21 PB09 PA04 VDDIO GND PA11 PA13 PA20 ATUC64/128/256L3U TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 Figure 3-3.
ATUC64/128/256L3/4U Peripheral Multiplexing on I/O lines 3.1.1 Multiplexed Signals Each GPIO line can be assigned to one of the peripheral functions. The following table describes the peripheral signals multiplexed to the GPIO lines. Table 3-1.
ATUC64/128/256L3/4U Table 3-1.
ATUC64/128/256L3/4U Table 3-1. 3.
ATUC64/128/256L3/4U 3.2.2 Peripheral Functions Each GPIO line can be assigned to one of several peripheral functions. The following table describes how the various peripheral functions are selected. The last listed function has priority in case multiple functions are enabled on the same pin. Table 3-2. 3.2.
ATUC64/128/256L3/4U Table 3-4. 3.2.5 Nexus OCD AUX Port Connections Pin AXS=1 AXS=0 EVTO_N PA04 PA04 MCKO PA06 PB01 MSEO[1] PA07 PB11 MSEO[0] PA11 PB12 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-5. 3.2.
ATUC64/128/256L3/4U 3.3 Signal Descriptions The following table gives details on signal name classified by peripheral. Table 3-7.
ATUC64/128/256L3/4U Table 3-7.
ATUC64/128/256L3/4U Table 3-7.
ATUC64/128/256L3/4U Table 3-8. Signal Description List, Continued Signal Name Function MSEO1 - MSEO0 Trace Frame Control EVTI_N Event In EVTO_N Event Out Type Active Level Comments Output Input Low Output Low General Purpose I/O pin PA22 - PA00 Parallel I/O Controller I/O Port 0 I/O PB27 - PB00 Parallel I/O Controller I/O Port 1 I/O Note: 1. See Section 6. on page 39 3.4 I/O Line Considerations 3.4.1 JTAG Pins The JTAG is enabled if TCK is low while the RESET_N pin is released.
ATUC64/128/256L3/4U 3.4.5 TWI Pins PA05/PA07/PA17 When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have the same characteristics as other GPIO pins. After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the GPIO Module Configuration chapter for details. 3.4.
ATUC64/128/256L3/4U 3.4.10 ADC Input Pins These pins are regular I/O pins powered from the VDDIO. However, when these pins are used for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins are not used for ADC inputs, the pins may be driven to the full I/O voltage range.
ATUC64/128/256L3/4U 4. Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, instruction set, and MPU is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 4.
ATUC64/128/256L3/4U single cycle. Load and store instructions have several different formats in order to reduce code size and speed up execution. The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 4.
ATUC64/128/256L3/4U OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 4-1. OCD system Power/ Reset control AVR32UC CPU pipeline MPU 4.3.
ATUC64/128/256L3/4U Figure 4-2. The AVR32UC Pipeline MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 4.3.2 Multiply unit Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers.
ATUC64/128/256L3/4U address exception. Doubleword-sized accesses with word-aligned pointers will automatically be performed as two word-sized accesses. The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 4-1. 4.3.2.5 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.
ATUC64/128/256L3/4U 4.4 4.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 4-3.
ATUC64/128/256L3/4U Figure 4-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 4.4.3 Processor States 4.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 4-2. Table 4-2. Overview of Execution Modes, their Priorities and Privilege Levels.
ATUC64/128/256L3/4U Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 4.4.3.3 4.4.4 Secure State The AVR32 can be set in a secure state, that allows a part of the code to execute in a state with higher security levels. The rest of the code can not access resources reserved for this secure code. Secure State is used to implement FlashVault technology. Refer to the AVR32UC Technical Reference Manual for details.
ATUC64/128/256L3/4U Table 4-3.
ATUC64/128/256L3/4U Table 4-3. 4.
ATUC64/128/256L3/4U relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes. The target address of the event handler is calculated as (EVBA | event_handler_offset), not (EVBA + event_handler_offset), so EVBA and exception code segments must be set up appropriately. The same mechanisms are used to service all different types of events, including interrupt requests, yielding a uniform event handling scheme.
ATUC64/128/256L3/4U 4.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes. The scall mechanism is designed so that a minimal execution cycle overhead is experienced when performing supervisor routine calls from timecritical event handlers.
ATUC64/128/256L3/4U than the oldest instruction. An instruction B is younger than an instruction A if it was sent down the pipeline later than A. The addresses and priority of simultaneous events are shown in Table 4-4 on page 34. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
ATUC64/128/256L3/4U Table 4-4.
ATUC64/128/256L3/4U 5. Memories 5.
ATUC64/128/256L3/4U 5.3 Peripheral Address Map Table 5-3. Peripheral Address Mapping Address Peripheral Name 0xFFFE0000 FLASHCDW Flash Controller - FLASHCDW 0xFFFE0400 HMATRIX HSB Matrix - HMATRIX 0xFFFE0800 SAU Secure Access Unit - SAU USBC USB 2.
ATUC64/128/256L3/4U Table 5-3.
ATUC64/128/256L3/4U The following GPIO registers are mapped on the local bus: Table 5-4.
ATUC64/128/256L3/4U 6. Supply and Startup Considerations 6.1 6.1.1 Supply Considerations Power Supplies The ATUC64/128/256L3/4U has several types of power supply pins: • VDDIO: Powers I/O lines. Voltage is 1.8 to 3.3V nominal. • VDDIN: Powers I/O lines, the USB pins, and the internal regulator. Voltage is 1.8 to 3.3V nominal if USB is not used, and 3.3V nominal when USB is used. • VDDANA: Powers the ADC. Voltage is 1.8V nominal. • VDDCORE: Powers the core, memories, and peripherals. Voltage is 1.
ATUC64/128/256L3/4U 6.1.3 Regulator Connection The ATUC64/128/256L3/4U supports three power supply configurations: • 3.3V single supply mode – Shutdown mode is not available • 1.8V single supply mode – Shutdown mode is not available • 3.3V supply mode, with 1.
ATUC64/128/256L3/4U 6.1.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin) and its output feeds VDDCORE. Figure 6-2 shows the power schematics to be used for 3.3V single supply mode. All I/O lines will be powered by the same power (VDDIN=VDDIO). Figure 6-2. 3.3V Single Supply Mode + 1.98-3.
ATUC64/128/256L3/4U 6.1.3.2 1.8V Single Supply Mode In 1.8V single supply mode the internal regulator is not used, and VDDIO and VDDCORE are powered by a single 1.8 V supply as shown in Figure 6-3. All I/O lines will be powered by the same power (VDDIN = VDDIO = VDDCORE). Figure 6-3. 1.8V Single Supply Mode + 1.62-1.
ATUC64/128/256L3/4U 6.1.3.3 3.3V Supply Mode with 1.8V Regulated I/O Lines In this mode, the internal regulator is connected to the 3.3V source and its output is connected to both VDDCORE and VDDIO as shown in Figure 6-4. This configuration is required in order to use Shutdown mode. Figure 6-4. 3.3V Supply Mode with 1.8V Regulated I/O Lines + 1.98-3.
ATUC64/128/256L3/4U 6.1.4 Power-up Sequence 6.1.4.1 Maximum Rise Rate To avoid risk of latch-up, the rise rate of the power supplies must not exceed the values described in Table 35-3 on page 898. Recommended order for power supplies is also described in this chapter. 6.1.4.2 Minimum Rise Rate The integrated Power-on Reset (POR33) circuitry monitoring the VDDIN powering supply requires a minimum rise rate for the VDDIN power supply. See Table 35-3 on page 898 for the minimum rise rate value.
ATUC64/128/256L3/4U 7. Peripheral DMA Controller (PDCA) Rev: 1.2.3.1 7.1 Features • • • • • • 7.
ATUC64/128/256L3/4U 7.3 Block Diagram Figure 7-1. PDCA Block Diagram Peripheral 0 Memory HSB to PB Bridge HSB Peripheral Bus HSB High Speed Bus Matrix HSB Interrupt Controller IRQ Peripheral 2 ... Peripheral DMA Controller (PDCA) Peripheral 1 Peripheral (n-1) Handshake Interfaces 7.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 7.4.
ATUC64/128/256L3/4U 7.4.4 7.5 7.5.1 Peripheral Events The PDCA peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. Functional Description Basic Operation The PDCA consists of multiple independent PDCA channels, each capable of handling DMA requests in parallel. Each PDCA channels contains a set of configuration registers which must be configured to start a DMA transfer.
ATUC64/128/256L3/4U If TCR is zero when writing to TCRR, the TCR and MAR are automatically updated with the value written in TCRR and MARR. 7.5.5 Ring Buffer When Ring Buffer mode is enabled the TCRR and MARR registers will not be cleared when TCR and MAR registers reload. This allows the PDCA to read or write to the same memory region over and over again until the transfer is actively stopped by the user. Ring Buffer mode is enabled by writing a one to the Ring Buffer bit in the Mode Register (MR.RING).
ATUC64/128/256L3/4U 7.5.10 Priority If more than one PDCA channel is requesting transfer at a given time, the PDCA channels are prioritized by their channel number. Channels with lower numbers have priority over channels with higher numbers, giving channel zero the highest priority. 7.5.11 Error Handling If the Memory Address Register (MAR) is set to point to an invalid location in memory, an error will occur when the PDCA tries to perform a transfer.
ATUC64/128/256L3/4U The registers can also be manually reset by writing a one to the Channel Reset bit in the PCONTROL register (PCONTROL.CH0/1RES). The Performance Channel Read/Write Latency registers (PRLAT0/1 and PWLAT0/1) are saturating when their maximum count value is reached. The PRLAT0/1 and PWLAT0/1 registers can only be reset by writing a one to the corresponding reset bit in PCONTROL (PCONTROL.CH0/1RES).
ATUC64/128/256L3/4U 7.7 User Interface 7.7.1 Memory Map Overview Table 7-1. PDCA Register Memory Map Address Range Contents 0x000 - 0x03F DMA channel 0 configuration registers 0x040 - 0x07F DMA channel 1 configuration registers ... ... (0x000 - 0x03F)+m*0x040 DMA channel m configuration registers 0x800-0x830 Performance Monitor registers 0x834 Version register The channels are mapped as shown in Table 7-1.
ATUC64/128/256L3/4U 7.7.3 Performance Monitor Memory Map PDCA Performance Monitor Registers(1) Table 7-3.
ATUC64/128/256L3/4U 7.7.5 Name: Memory Address Register MAR Access Type: Read/Write Offset: 0x000 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 MADDR[31:24] 23 22 21 20 19 MADDR[23:16] 15 14 13 12 MADDR[15:8] 7 6 5 4 MADDR[7:0] • MADDR: Memory Address Address of memory buffer. MADDR should be programmed to point to the start of the memory buffer when configuring the PDCA.
ATUC64/128/256L3/4U 7.7.6 Name: Peripheral Select Register PSR Access Type: Read/Write Offset: 0x004 + n*0x040 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PID • PID: Peripheral Identifier The Peripheral Identifier selects which peripheral should be connected to the DMA channel.
ATUC64/128/256L3/4U 7.7.7 Name: Transfer Counter Register TCR Access Type: Read/Write Offset: 0x008 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCV[15:8] 7 6 5 4 TCV[7:0] • TCV: Transfer Counter Value Number of data items to be transferred by the PDCA. TCV must be programmed with the total number of transfers to be made.
ATUC64/128/256L3/4U 7.7.8 Name: Memory Address Reload Register MARR Access Type: Read/Write Offset: 0x00C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MARV[31:24] 23 22 21 20 MARV[23:16] 15 14 13 12 MARV[15:8] 7 6 5 4 MARV[7:0] • MARV: Memory Address Reload Value Reload Value for the MAR register. This value will be loaded into MAR when TCR reaches zero if the TCRR register has a nonzero value.
ATUC64/128/256L3/4U 7.7.9 Name: Transfer Counter Reload Register TCRR Access Type: Read/Write Offset: 0x010 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 TCRV[15:8] 7 6 5 4 TCRV[7:0] • TCRV: Transfer Counter Reload Value Reload value for the TCR register. When TCR reaches zero, it will be reloaded with TCRV if TCRV has a positive value.
ATUC64/128/256L3/4U 7.7.10 Name: Control Register CR Access Type: Write-only Offset: 0x014 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ECLR 7 6 5 4 3 2 1 0 - - - - - - TDIS TEN • ECLR: Transfer Error Clear Writing a zero to this bit has no effect.
ATUC64/128/256L3/4U 7.7.11 Name: Mode Register MR Access Type: Read/Write Offset: 0x018 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - RING ETRIG SIZE • RING: Ring Buffer 0:The Ring buffer functionality is disabled. 1:The Ring buffer functionality is enabled.
ATUC64/128/256L3/4U 7.7.12 Name: Status Register SR Access Type: Read-only Offset: 0x01C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - TEN • TEN: Transfer Enabled This bit is cleared when the TDIS bit in CR is written to one. This bit is set when the TEN bit in CR is written to one.
ATUC64/128/256L3/4U 7.7.13 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x020 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 7.7.14 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x024 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 7.7.15 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x028 + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 7.7.16 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x02C + n*0x040 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TERR TRC RCZ • TERR: Transfer Error This bit is cleared when no transfer errors have occurred since the last write to CR.ECLR.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.20 Name: Performance Channel 0 Read Max Latency PRLAT0 Access Type: Read/Write Offset: 0x80C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.23 Name: Performance Channel 0 Write Max Latency PWLAT0 Access Type: Read/Write Offset: 0x818 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.26 Name: Performance Channel 1 Read Max Latency PRLAT1 Access Type: Read/Write Offset: 0x824 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.
ATUC64/128/256L3/4U 7.7.29 Name: Performance Channel 1 Write Max Latency PWLAT1 Access Type: Read/Write Offset: 0x830 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 LAT[15:8] 7 6 5 4 LAT[7:0] • LAT: Maximum Transfer Initiation Cycles Counted Since Last Reset Clock cycles are counted using the CLK_PDCA_HSB clock This counter is saturating.
ATUC64/128/256L3/4U 7.7.30 Name: PDCA Version Register VERSION Access Type: Read-only Offset: 0x834 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 7.8 Module Configuration The specific configuration for each PDCA instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 7-6. PDCA Configuration Feature PDCA Number of channels 12 Number of performance monitors 1 Table 7-7.
ATUC64/128/256L3/4U Table 7-9.
ATUC64/128/256L3/4U 8. USB Interface (USBC) Rev: 2.0.0.15 8.1 Features • • • • • • • 8.2 Compatible with the USB 2.0 specification Supports full (12Mbit/s) and low (1.
ATUC64/128/256L3/4U • User interface • USB Core • Transceiver pads Figure 8-1. USBC Block Diagram USB HSB HSB Master USB_VBUS PB DM User interface USB 2.0 Core DP USB interrupts Interrupt Controller SCIF (1) GCLK_USBC @ 48 MHz System clock USB clock domain domain Note: in the block diagram is symbolic, it is mapped to a GPIO pin (See Section “8.5.1” on page 84.). The VBUS detection (rising edge detection on the GPIO pin) should be handled by software.
ATUC64/128/256L3/4U 8.4 I/O Lines Description Table 8-2.
ATUC64/128/256L3/4U 8.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 8.5.1 I/O Lines The USBC pins may be multiplexed with the I/O Controller lines. The user must first configure the I/O Controller to assign the desired USBC pins to their peripheral functions. The USB VBUS line should be connected to a GPIO pin and the user should monitor this with software. 8.5.
ATUC64/128/256L3/4U 8.6 Functional Description 8.6.1 USB General Operation 8.6.1.1 Initialization After a hardware reset, the USBC is in the Reset state. In this state: • The module is disabled. The USBC Enable bit in the General Control register (USBCON.USBE) is reset. • The module clock is stopped in order to minimize power consumption. The Freeze USB Clock bit in USBCON (USBCON.FRZCLK) is set. • The USB pad is in suspend mode. • The internal states and registers of the device are reset.
ATUC64/128/256L3/4U Figure 8-2. Speed Selection in device mode RPU VBUS UDCON.DETACH UDCON.LS DP DM 8.6.1.5 Data management Endpoints and pipe buffers can be allocated anywhere in the embedded memory (CPU RAM or HSB RAM). See ”RAM management” on page 90. 8.6.1.6 Pad Suspend Figure 8-3 illustrates the behavior of the USB pad in device mode. Figure 8-3.
ATUC64/128/256L3/4U Figure 8-4. Pad events SUSP Suspend detected WAKEUP Cleared on Wakeup Wakeup detected Cleared by software to acknowledge the interrupt PAD state Active Idle Active The Suspend Interrupt bit in the Device Global Interrupt register (UDINT.SUSP) is set and the Wakeup Interrupt (UDINT.WAKEUP) bit is cleared when a USB Suspend state has been detected on the USB bus. This event automatically puts the USB pad in the Idle state.
ATUC64/128/256L3/4U 8.6.2 USBC Device Mode Operation 8.6.2.1 Device Enabling In device mode, the USBC supports full- and low-speed data transfers. Including the default control endpoint, a total of seven endpoints are provided. They can be configured as isochronous, bulk or interrupt types, as described in Table 8-1 on page 81 After a hardware reset, the USBC device mode is in the reset state (see Section 8.6.1.1).
ATUC64/128/256L3/4U • After all kinds of resets, the USB device address is 0. • The host starts a SETUP transaction with a SET_ADDRESS(addr) request. • The user writes this address to the USB Address field (UDCON.UADD), and writes a zero to the Address Enable bit (UDCON.ADDEN), resulting in the address remaining zero. • The user sends a zero-length IN packet from the control endpoint. • The user enables the stored USB device address by writing a one to ADDEN.
ATUC64/128/256L3/4U • The user may then write a one to the remote wakeup (RMWKUP) bit in UDCON to send an Upstream Resume to the host initiating the wakeup. This will automatically be done by the controller after 5ms of inactivity on the USB bus. • When the controller sends the Upstream Resume, the Upstream Resume (UPRSM) interrupt is set and SUSP is cleared. • RMWKUP is cleared at the end of the transmitting Upstream Resume.
ATUC64/128/256L3/4U Figure 8-5.
ATUC64/128/256L3/4U • The control and status fields for the endpoint and bank (EPn_CTR_STA_BK0/1): Table 8-4. 31:19 EPn_CTR_STA_BK0/1 structure 18 17 16 15:1 Status elements - UNDERF OVERF 0 Control elements CRCERR - STALLRQ_NEXT – UNDERF: Underflow status for isochronous IN transfer. See ”Data flow error” on page 99. – OVERF: Overflow status for isochronous OUT transfer. See ”Data flow error” on page 99. – CRCERR: CRC error status for isochronous OUT transfer. See ”CRC error” on page 99.
ATUC64/128/256L3/4U 8.6.2.12 Multi packet mode and single packet mode. Single packet mode is the default mode where one USB packet is managed per bank. The multi-packet mode allows the user to manage data exceeding the maximum endpoint size (UECFGn.EPSIZE) for an endpoint bank across multiple packets without software intervention. This mode can also be coupled with the ping-pong mode. • For an OUT endpoint, the EPn_PCKSIZE_BK0/1.
ATUC64/128/256L3/4U Figure 8-6. Control Write SETUP USB Bus DATA SETUP OUT STATUS OUT IN IN NAK RXSTPI HW SW RXOUTI HW SW HW SW TXINI SW • Control read Figure 8-7 on page 94 shows a control read transaction. The USBC has to manage the simultaneous write requests from the CPU and USB host. Figure 8-7.
ATUC64/128/256L3/4U 8.6.2.14 Management of IN endpoints • Overview IN packets are sent by the USBC device controller upon IN requests from the host. The endpoint and its descriptor in RAM must be pre configured (see section ”RAM management” on page 90 for more details). When the current bank is clear, the TXINI and FIFO Control (UECONn.FIFOCON) bits will be set simultaneously. This triggers an EPnINT interrupt if the Transmitted IN Data Interrupt Enable (TXINE) bit in UECONn is one.
ATUC64/128/256L3/4U • Detailed description The data is written according to this sequence: • When the bank is empty, TXINI and FIFOCON are set, which triggers an EPnINT interrupt if TXINE is one. • The user acknowledges the interrupt by clearing TXINI. • The user reads the UESTAX.CURRBK field to see which the current bank is. • The user writes the data to the current bank, located in RAM as described by its descriptor: EPn_ADDR_BK0/1.
ATUC64/128/256L3/4U set, or if the total byte count is not an integral multiple of EPSIZE, whereby the last packet should be short. To enable the multi packet mode, the user should configure the endpoint descriptor (EPn_PCKSIZE_BK0/1.BYTE_COUNT) to the total size of the multi packet, which should be larger than the endpoint size (EPSIZE). Since the EPn_PCKSIZE_BK0/1.
ATUC64/128/256L3/4U Figure 8-12. Example of an OUT endpoint with two data banks OUT DATA (bank 0) ACK OUT DATA (bank 1) HW RXOUTI ACK HW SW SW read data from CPU BANK 0 FIFOCON SW read data from CPU BANK 1 • Detailed description Before using the OUT endpoint, one should properly initialize its descriptor for each bank. See Figure 8-5 on page 91.
ATUC64/128/256L3/4U • A packet has been successfully received and the updated BYTE_COUNT equals the MULTI_PACKET_SIZE. • A short packet (smaller than EPSIZE) has been received. 8.6.2.16 Data flow error This error exists only for isochronous IN/OUT endpoints. It sets the Errorflow Interrupt (ERRORFI) bit in UESTAn, which triggers an EPnINT interrupt if the Errorflow Interrupt Enable (ERRORFE) bit is one. The user can check the EPn_CTR_STA_BK0/1.
ATUC64/128/256L3/4U • The Start of Frame (SOF) interrupt with a frame number CRC error (FNCERR is one) • Endpoint interrupts The processing device endpoint interrupts are: • The Transmitted IN Data Interrupt (TXINI) • The Received OUT Data Interrupt (RXOUTI) • The Received SETUP Interrupt (RXSTPI) • The Number of Busy Banks (NBUSYBK) interrupt The exception device endpoint interrupts are: • The Errorflow Interrupt (ERRORFI) • The NAKed OUT Interrupt (NAKOUTI) • The NAKed IN Interrupt (NAKINI) • The STALLed
ATUC64/128/256L3/4U 8.7 User Interface Table 8-5.
ATUC64/128/256L3/4U 8.7.1 USB General Registers 8.7.1.1 Name: General Control Register USBCON Access Type: Read/Write Offset: 0x0800 Reset Value: 0x00004000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 11 10 9 8 USBE FRZCLK - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - - - • USBE: USBC Enable Writing a zero to this bit will disable the USBC, USB transceiver, and USB clock inputs.
ATUC64/128/256L3/4U 8.7.1.2 General Status Register Register Name: USBSTA Access Type: Read-Only Offset: 0x0804 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CLKUSABLE - - - - 7 6 5 4 3 2 1 0 - - - - - - - - SPEED • CLKUSABLE: Generic Clock Usable This bit is cleared when the USB generic clock is not usable.
ATUC64/128/256L3/4U 8.7.1.3 General Status Clear Register Register Name: USBSTACLR Access Type: Write-Only Offset: 0x0808 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in USBSTA.
ATUC64/128/256L3/4U 8.7.1.4 General Status Set Register Register Name: USBSTASET Access Type: Write-Only Offset: 0x080C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in USBSTA.
ATUC64/128/256L3/4U 8.7.1.5 Version Register Register Name: UVERS Access Type: Read-Only Offset: 0x0818 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 8.7.1.
ATUC64/128/256L3/4U 8.7.1.7 Address Size Register Register Name: UADDRSIZE Access Type: Read-Only Offset: 0x0820 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UADDRSIZE[31:24] 23 22 21 20 19 UADDRSIZE[23:16] 15 14 13 12 11 UADDRSIZE[15:8] 7 6 5 4 3 UADDRSIZE[7:0] • UADDRSIZE: IP PB Address Size This field indicates the size of the PB address space reserved for the USBC IP interface.
ATUC64/128/256L3/4U 8.7.1.8 IP Name Register 1 Register Name: UNAME1 Access Type: Read-Only Offset: 0x0824 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME1[31:24] 23 22 21 20 19 UNAME1[23:16] 15 14 13 12 11 UNAME1[15:8] 7 6 5 4 3 UNAME1[7:0] • UNAME1: IP Name Part One This field indicates the first part of the ASCII-encoded name of the USBC IP.
ATUC64/128/256L3/4U 8.7.1.9 IP Name Register 2 Register Name: UNAME2 Access Type: Read-Only Offset: 0x0828 Reset Value: 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UNAME2[31:24] 23 22 21 20 19 UNAME2[23:16] 15 14 13 12 11 UNAME2[15:8] 7 6 5 4 3 UNAME2[7:0] • UNAME2: IP Name Part Two This field indicates the second part of the ASCII-encoded name of the USBC IP.
ATUC64/128/256L3/4U 8.7.1.10 Finite State Machine Status Register Register Name: USBFSM Access Type: Read-Only Offset: 0x082C Reset Value: 0x00000009 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - DRDSTATE • DRDSTATE: Dual Role Device State This field indicates the state of the USBC. For Device mode it should always read 9.
ATUC64/128/256L3/4U 8.7.1.11 USB Descriptor Address Register Name: UDESC Access Type: Read-Write Offset: 0x0830 Reset Value: - 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 UDESCA[31:24] 23 22 21 20 19 UDESCA[23:16] 15 14 13 12 11 UDESCA[15:8] 7 6 5 4 3 UDESCA[7:0] • UDESCA: USB Descriptor Address This field contains the address of the USB descriptor. The three least significant bits are always zero.
ATUC64/128/256L3/4U 8.7.2 USB Device Registers 8.7.2.1 Device General Control Register Register Name: UDCON Access Type: Read/Write Offset: 0x0000 Reset Value: 0x00000100 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - GNAK - 15 14 13 12 11 10 9 8 - - - LS - - RMWKUP DETACH 7 6 5 4 3 2 1 0 ADDEN UADD • GNAK: Global NAK 0: Normal mode.
ATUC64/128/256L3/4U 8.7.2.2 Device Global Interrupt Register Register Name: UDINT Access Type: Read-Only Offset: 0x0004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 18 (1) EP7INT EP6INT 17 (1) EP5INT 16 (1) EP4INT(1) - - - 15 14 13 12 11 10 9 8 EP3INT(1) EP2INT(1) EP1INT(1) EP0INT - - - - 7 6 5 4 3 2 1 0 - UPRSM EORSM WAKEUP EORST SOF - SUSP Note: EP8INT 19 (1) 1.
ATUC64/128/256L3/4U • SUSP: Suspend Interrupt This bit is cleared when the UDINTCLR.SUSPC bit is written to one to acknowledge the interrupt or when the Wakeup (WAKEUP) interrupt bit is set. This bit is set when a USB “Suspend” idle bus state has been detected for 3 frame periods (J state for 3 ms). This triggers a USB interrupt if SUSPE is one.
ATUC64/128/256L3/4U 8.7.2.3 Device Global Interrupt Clear Register Register Name: UDINTCLR Access Type: Write-Only Offset: 0x0008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMC EORSMC WAKEUPC EORSTC SOFC - SUSPC Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 8.7.2.4 Device Global Interrupt Set Register Register Name: UDINTSET Access Type: Write-Only Offset: 0x000C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - UPRSMS EORSMS WAKEUPS EORSTS SOFS - SUSPS Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 8.7.2.5 Device Global Interrupt Enable Register Register Name: UDINTE Access Type: Read-Only Offset: 0x0010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 (1) EP7INTE 17 (1) EP6INTE 16 (1) EP5INTE EP4INTE(1) - - - 15 14 13 12 11 10 9 8 EP3INTE(1) EP2INTE(1) EP1INTE(1) EP0INTE - - - - 7 6 5 4 3 2 1 0 - UPRSME EORSME WAKEUPE EORSTE SOFE - SUSPE Note: EP8INTE 18 (1) 1.
ATUC64/128/256L3/4U 8.7.2.
ATUC64/128/256L3/4U 8.7.2.
ATUC64/128/256L3/4U 8.7.2.8 Endpoint Enable/Reset Register Register Name: UERST Access Type: Read/Write Offset: 0x001C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - EPEN8(1) 7 6 5 4 3 2 1 0 EPEN7(1) EPEN6(1) EPEN5(1) EPEN4(1) EPEN3(1) EPEN2(1) EPEN1(1) EPEN0 • EPENn: Endpoint n Enable Note: 1.
ATUC64/128/256L3/4U 8.7.2.9 Device Frame Number Register Register Name: UDFNUM Access Type: Read-Only Offset: 0x0020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 FNCERR - 7 6 2 1 0 - - - FNUM[10:5] 5 FNUM[4:0] 4 3 • FNCERR: Frame Number CRC Error This bit is cleared upon receiving a USB reset. This bit is set when a corrupted frame number is received.
ATUC64/128/256L3/4U 8.7.2.10 Endpoint n Configuration Register Register Name: UECFGn, n in [0..
ATUC64/128/256L3/4U EPSIZE Endpoint Size 1 0 1 256 bytes 1 1 0 512 bytes 1 1 1 1024 bytes This field is cleared upon receiving a USB reset (except for the endpoint 0). • EPBK: Endpoint Banks This bit selects the number of banks for the endpoint: 0: single-bank endpoint 1: double-bank endpoint For control endpoints, a single-bank endpoint shall be selected. This field is cleared upon receiving a USB reset (except for the endpoint 0).
ATUC64/128/256L3/4U 8.7.2.11 Endpoint n Status Register Register Name: UESTAn, n in [0..
ATUC64/128/256L3/4U For IN endpoints, this indicates the number of banks filled by the user and ready for IN transfers. When all banks are free an EPnINT interrupt will be triggered if NBUSYBKE is one. For OUT endpoints, this indicates the number of banks filled by OUT transactions from the host. When all banks are busy an EPnINT interrupt will be triggered if NBUSYBKE is one. • RAMACERI: Ram Access Error Interrupt This bit is cleared when the RAMACERIC bit is written to one, acknowledging the interrupt.
ATUC64/128/256L3/4U This bit is set, for control endpoints, when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPnINT interrupt if RXOUTE is one. This bit is set for isochronous, bulk and, interrupt OUT endpoints, at the same time as FIFOCON when the current bank is full. This triggers an EPnINT interrupt if RXOUTE is one. This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
ATUC64/128/256L3/4U 8.7.2.12 Endpoint n Status Clear Register Register Name: UESTAnCLR, n in [0..
ATUC64/128/256L3/4U 8.7.2.13 Endpoint n Status Set Register Register Name: UESTAnSET, n in [0..
ATUC64/128/256L3/4U 8.7.2.14 Endpoint n Control Register Register Name: UECONn, n in [0..
ATUC64/128/256L3/4U • KILLBK: Kill IN Bank • • • • • • • • • • This bit is cleared by hardware after the completion of the “kill packet procedure”. This bit is set when the KILLBKS bit is written to one, killing the last written bank. The user shall wait for this bit to be cleared before trying to process another IN packet. Caution: The bank is cleared when the “kill packet” procedure is completed by the USBC core: If the bank is really killed, the NBUSYBK field is decremented.
ATUC64/128/256L3/4U 8.7.2.15 Endpoint n Control Clear Register Register Name: UECONnCLR, n in [0..
ATUC64/128/256L3/4U 8.7.2.16 Endpoint n Control Set Register Register Name: UECONnSET, n in [0..
ATUC64/128/256L3/4U 8.8 Module Configuration The specific configuration for each USBC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 8-6. USBC Clocks Clock Name Description CLK_USBC_PB Clock for the USBC PB interface CLK_USBC_HSB Clock for the USBC HSB interface GCLK_USBC The generic clock used for the USBC is GCLK7 Table 8-7.
ATUC64/128/256L3/4U 9. Flash Controller (FLASHCDW) Rev: 1.2.0.0 9.1 Features • • • • • • • • • • • • • 9.
ATUC64/128/256L3/4U 9.3.4 9.4 9.4.1 Debug Operation When an external debugger forces the CPU into debug mode, the FLASHCDW continues normal operation. If the FLASHCDW is configured in a way that requires it to be periodically serviced by the CPU through interrupts or similar, improper operation or data loss may result during debugging.
ATUC64/128/256L3/4U also the other word in the same 64-bit location is read. The first word is output on the bus, and the other word is put into an internal buffer. If a read to a sequential address is to be performed in the next cycle, the buffered word is output on the bus, while the next 64-bit location is read from the flash memory. Thus, latency in 1 wait state mode is hidden for sequential fetches.
ATUC64/128/256L3/4U Figure 9-1. Memory Map for the Flash Memories Offset from base address Reserved User Page Reserved 0x0080 0000 Flash data array pw 0 Flash base address Flash with User Page All addresses are byte addresses 9.4.5 High Speed Read Mode The flash provides a High Speed Read Mode, offering slightly higher flash read speed at the cost of higher power consumption. Two dedicated commands, High Speed Read Mode Enable (HSEN) and High Speed Read Mode Disable (HSDIS) control the speed mode.
ATUC64/128/256L3/4U Figure 9-2. High Speed Mode Frequency 1 wait state 0 wait state Frequency limit for 0 wait state operation No Hi gh rm al Speed mode 9.4.6 Quick Page Read A dedicated command, Quick Page Read (QPR), is provided to read all words in an addressed page. All bits in all words in this page are AND’ed together, returning a 1-bit result. This result is placed in the Quick Page Read Result (QPRR) bit in Flash Status Register (FSR).
ATUC64/128/256L3/4U Figure 9-3.
ATUC64/128/256L3/4U The page buffer is not automatically reset after a page write. The programmer should do this manually by issuing the Clear Page Buffer flash command. This can be done after a page write, or before the page buffer is loaded with data to be stored to the flash page. 9.5 Flash Commands The FLASHCDW offers a command set to manage programming of the flash memory, locking and unlocking of regions, and full flash erasing. See Section 9.8.2 for a complete list of commands.
ATUC64/128/256L3/4U After programming, the page can be locked to prevent miscellaneous write or erase sequences. Locking is performed on a per-region basis, so locking a region locks all pages inside the region. Additional protection is provided for the lowermost address space of the flash. This address space is allocated for the Boot Loader, and is protected both by the lock bit(s) corresponding to this address space, and the BOOTPROT[2:0] fuses.
ATUC64/128/256L3/4U • Programming Error: A bad keyword and/or an invalid command have been written in the FCMD register. • Lock Error: At least one lock region is protected, or BOOTPROT is different from 0. The erase command has been aborted and no page has been erased. A “Unlock region containing given page” (UP) command must be executed to unlock any locked regions. 9.5.3 Region Lock Bits The flash memory has p pages, and these pages are grouped into 16 lock regions, each region containing p/16 pages.
ATUC64/128/256L3/4U through a dedicated Peripheral Bus address. Some of the general-purpose fuse bits are reserved for special purposes, and should not be used for other functions: Table 9-2. General-purpose Fuses with Special Functions GeneralPurpose fuse number Name Usage 15:0 LOCK Region lock bits. EPFL External Privileged Fetch Lock. Used to prevent the CPU from fetching instructions from external memories when in privileged mode. This bit can only be changed when the security bit is cleared.
ATUC64/128/256L3/4U Table 9-3. Boot Loader Area Specified by BOOTPROT BOOTPROT Pages protected by BOOTPROT Size of protected memory 7 None 0 6 0-1 1Kbyte 5 0-3 2Kbyte 4 0-7 4Kbyte 3 0-15 8Kbyte 2 0-31 16Kbyte 1 0-63 32Kbyte 0 0-127 64Kbyte The SECURE fuses have the following functionality: Table 9-5.
ATUC64/128/256L3/4U 9.7 Security Bit The security bit allows the entire device to be locked from external JTAG, aWire, or other debug access for code security. The security bit can be written by a dedicated command, Set Security Bit (SSB). Once set, the only way to clear the security bit is through the JTAG or aWire Chip Erase command.
ATUC64/128/256L3/4U 9.8 User Interface Table 9-6.
ATUC64/128/256L3/4U 9.8.1 Name: Flash Control Register FCR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - BRBUF SEQBUF - 7 6 5 4 3 2 1 0 - FWS - - PROGE LOCKE - FRDY • BRBUF: Branch Target Instruction Buffer Enable 0: The Branch Target Instruction Buffer is disabled.
ATUC64/128/256L3/4U 9.8.2 Name: Flash Command Register FCMD Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 The FCMD can not be written if the flash is in the process of performing a flash command. Doing so will cause the FCR write to be ignored, and the PROGE bit in FSR to be set.
ATUC64/128/256L3/4U Table 9-7. Semantic of PAGEN field in different commands Command PAGEN description Program GP Fuse Byte WriteData[7:0], ByteAddress[2:0] Erase All GP Fuses Not used Quick Page Read Page number Write User Page Not used Erase User Page Not used Quick Page Read User Page Not used High Speed Mode Enable Not used High Speed Mode Disable Not used • CMD: Command This field defines the flash command.
ATUC64/128/256L3/4U 9.8.
ATUC64/128/256L3/4U 9.8.4 Name: Flash Parameter Register FPR Access Type: Read-only Offset: 0x0C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 - - - - PSZ 2 1 0 FSZ • PSZ: Page Size The size of each flash page. Table 9-9.
ATUC64/128/256L3/4U • FSZ: Flash Size The size of the flash. Not all device families will provide all flash sizes indicated in the table. Table 9-10.
ATUC64/128/256L3/4U 9.8.5 Name: Flash Version Register FVR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 9.8.
ATUC64/128/256L3/4U 9.8.
ATUC64/128/256L3/4U 9.9 Fuse Settings The flash contains 32 general purpose fuses. These 32 fuses can be found in the Flash General Purpose Fuse Register Low (FGPFRLO). The Flash General Purpose Fuse Register High (FGPFRHI) is not used. In addition to the general purpose fuses, parts of the flash user page can have a defined meaning outside of the flash controller and will also be described in this section.
ATUC64/128/256L3/4U 9.9.
ATUC64/128/256L3/4U 9.9.2 First Word of the User Page (Address 0x80800000) 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - WDTAUTO • WDTAUTO: WatchDog Timer Auto Enable at Startup 0: The WDT is automatically enabled at startup. 1: The WDT is not automatically enabled at startup.
ATUC64/128/256L3/4U 9.9.3 Second Word of the User Page (Address 0x80800004) 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SSADRR[15:8] 23 22 21 20 SSADRR[7:0] 15 14 13 12 SSADRF[15:8] 7 6 5 4 SSADRF[7:0] • SSADRR: Secure State End Address for the RAM • SSADRF: Secure State End Address for the Flash 9.9.3.1 Default user page second word value The devices are shipped with the User page erased (all bits 1). 9.
ATUC64/128/256L3/4U Table 9-13.
ATUC64/128/256L3/4U 10. Secure Access Unit (SAU) Rev: 1.1.1.3 10.
ATUC64/128/256L3/4U 10.3 Block Diagram Figure 10-1 presents the SAU integrated in an example system with a CPU, some memories, some peripherals, and a bus system. The SAU is connected to both the Peripheral Bus (PB) and the High Speed Bus (HSB). Configuration of the SAU is done via the PB, while memory accesses are done via the HSB.
ATUC64/128/256L3/4U 10.4 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 10.4.1 Power Management If the CPU enters a sleep mode that disables clocks used by the SAU, the SAU will stop functioning and resume operation after the system wakes up from sleep mode. 10.4.2 Clocks The SAU has two bus clocks connected: One High Speed Bus clock (CLK_SAU_HSB) and one Peripheral Bus clock (CLK_SAU_PB).
ATUC64/128/256L3/4U 10.5.2.1 10.5.3 Protecting SAU configuration registers In order to prevent the SAU configuration registers to be changed by malicious or runaway code, they should be protected by the MPU as soon as they have been configured. Maximum security is provided in the system if program memory does not contain any code to unprotect the configuration registers in the MPU. This guarantees that runaway code can not accidentally unprotect and thereafter change the SAU configuration registers.
ATUC64/128/256L3/4U 10.5.4.1 Operation example Figure 10-2 shows a typical memory map, consisting of some memories, some simple peripherals, and a SAU with multiple channels and an Unlock Register (UR). Imagine that the MPU has been set up to disallow all accesses from the CPU to the grey modules. Thus the CPU has no way of accessing for example the Transmit Holding register in the UART, present on address X on the bus. Note that the SAU RTRs are not protected by the MPU, thus the RTRs can be accessed.
ATUC64/128/256L3/4U • Unlock Register Error Status (URES) is set if an attempt was made to unlock a channel by writing to the Unlock Register while one or more error bits in SR were set (see Section 10.5.6). The unlock operation was aborted. • Unlock Register Key Error (URKEY) is set if the Unlock Register was attempted written with an invalid key. • Unlock Register Read (URREAD) is set if the Unlock Register was attempted read.
ATUC64/128/256L3/4U 10.6 User Interface The following addresses are used by SAU channel configuration registers. All offsets are relative to the SAU’s PB base address. Table 10-1.
ATUC64/128/256L3/4U 10.6.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - BERRDIS BERREN SDIS SEN DIS EN • BERRDIS: Bus Error Response Disable Writing a zero to this bit has no effect. Writing a one to this bit disables Bus Error Response from the SAU.
ATUC64/128/256L3/4U 10.6.2 Name: Configuration Register CONFIG Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OPEN 15 14 13 12 11 10 9 8 3 2 1 0 UCYC 7 6 5 4 UKEY • OPEN: Open Mode Enable Writing a zero to this bit disables open mode. Writing a one to this bit enables open mode.
ATUC64/128/256L3/4U 10.6.3 Name: Channel Enable Register High CERH Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 - 23 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CERH[30:24] 22 21 20 CERH[23:16] 15 14 13 12 CERH[15:8] 7 6 5 4 CERH[7:0] • CERH[n]: Channel Enable Register High 0: Channel (n+32) is not enabled. 1: Channel (n+32) is enabled.
ATUC64/128/256L3/4U 10.6.4 Name: Channel Enable Register Low CERL Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CERL[31:24] 23 22 21 20 CERL[23:16] 15 14 13 12 CERL[15:8] 7 6 5 4 CERL[7:0] • CERL[n]: Channel Enable Register Low 0: Channel n is not enabled. 1: Channel n is enabled.
ATUC64/128/256L3/4U 10.6.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000400 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - IDLE SEN EN 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP • IDLE • • • • • • • This bit is cleared when a read or write operation to the SAU channel is started.
ATUC64/128/256L3/4U • CAU: Channel Access Unsuccessful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access was unsuccessful, i.e. an access was attempted to a locked or disabled channel. • CAS: Channel Access Successful This bit is cleared when the corresponding bit in ICR is written to one. This bit is set if channel access successful, i.e. one access was made after the channel was unlocked.
ATUC64/128/256L3/4U 10.6.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 10.6.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 10.6.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 10.6.9 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RTRADR MBERROR URES URKEY URREAD CAU CAS EXP Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 10.6.10 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x24 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CHANNELS • CHANNELS: Number of channels implemented.
ATUC64/128/256L3/4U 10.6.11 Name: Version Register VERSION Access Type: Write-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 10.6.
ATUC64/128/256L3/4U 10.6.13 Name: Unlock Register UR Access Type : Write-only Offset: 0xFC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 KEY 7 6 - - 5 4 CHANNEL • KEY: Unlock Key The correct key must be written in order to unlock a channel. The key value written must correspond to the key value defined in CONFIG.UKEY.
ATUC64/128/256L3/4U 10.7 Module Configuration The specific configuration for each SAU instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 10-3. SAU configuration Feature SAU SAU Channels 16 Table 10-4. SAU clock name Module name Clock name Description SAU CLK_SAU_HSB Clock for the SAU HSB interface SAU CLK_SAU_PB Clock for the SAU PB interface Table 10-5.
ATUC64/128/256L3/4U 11. HSB Bus Matrix (HMATRIXB) Rev: 1.3.0.3 11.1 Features • • • • • • • • • 11.
ATUC64/128/256L3/4U To change from one kind of default master to another, the Bus Matrix user interface provides the Slave Configuration Registers, one for each slave, that set a default master for each slave. The Slave Configuration Register contains two fields: DEFMSTR_TYPE and FIXED_DEFMSTR.
ATUC64/128/256L3/4U • Undefined Length Burst Arbitration In order to avoid long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in order to re-arbitrate before the end of the INCR transfer. A predicted end of burst is used as a defined length burst transfer and can be selected among the following five possibilities: 1. Infinite: No predicted end of burst is generated and therefore INCR burst transfer will never be broken. 2.
ATUC64/128/256L3/4U rent transfer, if no other master request is pending, the slave remains connected to the last master that performed the access. Other non privileged masters still get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform single accesses. • Round-Robin Arbitration with Fixed Default Master This is another biased round-robin algorithm.
ATUC64/128/256L3/4U 11.5 User Interface Table 11-1.
ATUC64/128/256L3/4U Table 11-1.
ATUC64/128/256L3/4U Table 11-1.
ATUC64/128/256L3/4U 11.5.1 Name: Master Configuration Registers MCFG0...MCFG15 Access Type: Read/Write Offset: 0x00 - 0x3C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – ULBT • ULBT: Undefined Length Burst Type Table 11-2.
ATUC64/128/256L3/4U 11.5.2 Name: Slave Configuration Registers SCFG0...
ATUC64/128/256L3/4U 11.5.3 Bus Matrix Priority Registers A For Slaves Register Name: PRAS0...PRAS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M7PR 21 20 M5PR 13 12 M3PR 5 4 M1PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M6PR 17 16 M4PR 9 8 M2PR 1 0 M0PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
ATUC64/128/256L3/4U 11.5.4 Name: Priority Registers B For Slaves PRBS0...PRBS15 Access Type: Read/Write Offset: - Reset Value: 0x00000000 31 30 - - 23 22 - - 15 14 - - 7 6 - - 29 28 M15PR 21 20 M13PR 13 12 M11PR 5 4 M9PR 27 26 - - 19 18 - - 11 10 - - 3 2 - - 25 24 M14PR 17 16 M12PR 9 8 M10PR 1 0 M8PR • MxPR: Master x Priority Fixed priority of Master x for accessing the selected slave. The higher the number, the higher the priority.
ATUC64/128/256L3/4U 11.5.5 Name: Special Function Registers SFR0...SFR15 Access Type: Read/Write Offset: 0x110 - 0x14C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SFR 23 22 21 20 SFR 15 14 13 12 SFR 7 6 5 4 SFR • SFR: Special Function Register Fields Those registers are not a HMATRIX specific register. The field of those will be defined where they are used.
ATUC64/128/256L3/4U 11.6 Module Configuration The specific configuration for each HMATRIX instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 11-3. 11.6.1 HMATRIX Clocks Clock Name Description CLK_HMATRIX Clock for the HMATRIX bus interface Bus Matrix Connections The bus matrix has the several masters and slaves.
ATUC64/128/256L3/4U Figure 11-1.
ATUC64/128/256L3/4U 12. Interrupt Controller (INTC) Rev: 1.0.2.5 12.1 Features • Autovectored low latency interrupt service with programmable priority – 4 priority levels for regular, maskable interrupts – One Non-Maskable Interrupt • Up to 64 groups of interrupts with up to 32 interrupt requests in each group 12.2 Overview The INTC collects interrupt requests from the peripherals, prioritizes them, and delivers an interrupt request and an autovector to the CPU.
ATUC64/128/256L3/4U Figure 12-1. INTC Block Diagram Interrupt Controller CPU NMIREQ Masks OR IRRn GrpReqN IREQ63 IREQ34 IREQ33 IREQ32 OR GrpReq1 INT_level, offset IPRn . . . Request Masking ValReq1 INT_level, offset IPR1 . . . INTLEVEL Prioritizer . . . ValReqN SREG Masks I[3-0]M GM AUTOVECTOR IRR1 IREQ31 IREQ2 IREQ1 IREQ0 OR GrpReq0 ValReq0 IPR0 INT_level, offset IRR0 IRR Registers 12.
ATUC64/128/256L3/4U Interrupt Priority Register (IPR). The GrpReq inputs are then masked by the mask bits from the CPU status register. Any interrupt group that has a pending interrupt of a priority level that is not masked by the CPU status register, gets its corresponding ValReq line asserted. Masking of the interrupt requests is done based on five interrupt mask bits of the CPU status register, namely Interrupt Level 3 Mask (I3M) to Interrupt Level 0 Mask (I0M), and Global Interrupt Mask (GM).
ATUC64/128/256L3/4U pipeline stall, which prevents the interrupt from accidentally re-triggering in case the handler is exited and the interrupt mask is cleared before the interrupt request is cleared.
ATUC64/128/256L3/4U 12.6 User Interface Table 12-1. INTC Register Memory Map Offset Register Register Name Access Reset 0x000 Interrupt Priority Register 0 IPR0 Read/Write 0x00000000 0x004 Interrupt Priority Register 1 IPR1 Read/Write 0x00000000 ... ... ... ... ... 0x0FC Interrupt Priority Register 63 IPR63 Read/Write 0x00000000 0x100 Interrupt Request Register 0 IRR0 Read-only N/A 0x104 Interrupt Request Register 1 IRR1 Read-only N/A ... ... ... ... ...
ATUC64/128/256L3/4U 12.6.1 Name: Interrupt Priority Registers IPR0...
ATUC64/128/256L3/4U 12.6.2 Name: Interrupt Request Registers IRR0...
ATUC64/128/256L3/4U 12.6.3 Name: Interrupt Cause Registers ICR0...ICR3 Access Type: Read-only Offset: 0x200 - 0x20C Reset Value: N/A 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CAUSE • CAUSE: Interrupt Group Causing Interrupt of Priority n ICRn identifies the group with the highest priority that has a pending interrupt of level n.
ATUC64/128/256L3/4U 12.7 Module Configuration The specific configuration for each INTC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 12-2. 12.7.1 12.8 INTC Clock Name Module Name Clock Name Description INTC CLK_INTC Clock for the INTC bus interface Interrupt Request Signal Map Interrupt Request Signal Map The various modules may output Interrupt request signals.
ATUC64/128/256L3/4U Table 12-3.
ATUC64/128/256L3/4U Table 12-3. Interrupt Request Signal Map 0 Timer/Counter TC10 1 Timer/Counter TC11 2 Timer/Counter TC12 27 0 ADC Interface ADCIFB 28 0 Analog Comparator Interface 29 0 Capacitive Touch Module CAT 30 0 aWire AW 31 0 Audio Bitstream DAC 32 0 USB 2.
ATUC64/128/256L3/4U 13. Power Manager (PM) Rev: 4.2.0.4 13.1 Features • • • • • • • 13.
ATUC64/128/256L3/4U 13.3 Block Diagram Figure 13-1. PM Block Diagram Main Clock Sources Synchronous Clock Generator Synchronous clocks CPU, HSB, PBx Interrupts Sleep Controller Sleep Instruction Reset Controller Resets Reset Sources Power-on Reset Detector(s) External Reset Pin 13.4 I/O Lines Description Table 13-1. I/O Lines Description Name Description Type Active Level RESET_N Reset Input Low 13.5 13.5.
ATUC64/128/256L3/4U 13.6 Functional Description 13.6.1 Synchronous Clocks The System RC Oscillator (RCSYS) and a selection of other clock sources can provide the source for the main clock, which is the origin for the synchronous CPU/HSB and PBx module clocks. For details about the other main clock sources, please refer to the Main Clock Control (MCCTRL) register description. The synchronous clocks can run of the main clock and all the 8bit prescaler settings as long as fCPU fPBx,.
ATUC64/128/256L3/4U Similarly, the PBx clocks can be divided by writing their respective Clock Select (PBxSEL) registers to get the divided PBx frequency: fPBx = fmain / 2(PBSEL+1) The PBx clock frequency can not exceed the CPU clock frequency. The user must select a PBxSEL.PBSEL value greater than or equal to the CPUSEL.CPUSEL value, so that fCPU fPBx. If the user selects division factors that will result in fCPU< fPBx, the Power Manager will automatically change the PBxSEL.
ATUC64/128/256L3/4U 13.6.3.1 Entering and exiting sleep modes The sleep instruction will halt the CPU and all modules belonging to the stopped clock domains. The modules will be halted regardless of the bit settings in the mask registers. Clock sources can also be switched off to save power. Some of these have a relatively long start-up time, and are only switched off when very low power consumption is required. The CPU and affected modules are restarted when the sleep mode is exited.
ATUC64/128/256L3/4U 13.6.3.3 Waking from sleep modes There are two types of wake-up sources from sleep mode, synchronous and asynchronous. Synchronous wake-up sources are all non-masked interrupts. Asynchronous wake-up sources are AST, WDT, external interrupts from EIC, external reset, external wake pin (WAKE_N), and all asynchronous wake-ups enabled in the Asynchronous Wake Up Enable (AWEN) register. The valid wake-up sources for each sleep mode are detailed in Table 13-3 on page 214.
ATUC64/128/256L3/4U Communication between the synchronous clock domains is disturbed when entering and exiting sleep modes. Bus transactions over clock domains affected by the sleep mode are therefore not recommended. The system may hang if the bus clocks are stopped during a bus transaction. The CPU is automatically stopped in a safe state to ensure that all CPU bus operations are complete when the sleep mode goes into effect. Thus, when entering Idle mode, no further action is necessary.
ATUC64/128/256L3/4U – The POR33 must be masked to avoid spurious resets when the power is back. This must also be done when POR33 is disabled, as POR33 will be enabled automatically when the device wakes up from Shutdown mode. Disable the POR33 by writing a one to the POR33MASK bit in the SCIF.VREGCR register. Due to internal synchronisation, this bit must be read as a one before the sleep instruction is executed by the CPU. Refer to the System Control Interface (SCIF) chapter for more details.
ATUC64/128/256L3/4U 13.6.6 Reset Controller The Reset Controller collects the various reset sources in the system and generates hard and soft resets for the digital logic. The device contains a Power-on Reset (POR) detector, which keeps the system reset until power is stable. This eliminates the need for external reset circuitry to guarantee stable operation when powering up the device. It is also possible to reset the device by pulling the RESET_N pin low.
ATUC64/128/256L3/4U Reset Source Description SM33 Reset Internal regulator supply voltage below the SM33 threshold voltage. This generates a Power-on Reset. Watchdog Timer See Watchdog Timer documentation OCD See On-Chip Debug documentation Depending on the reset source, when a reset occurs, some parts of the device are not always reset. Only the Power-on Reset (POR) will force a whole device reset.
ATUC64/128/256L3/4U – A lock protected register is written to without first being unlocked. • CKRDY - Clock Ready: – New Clock Select settings in the CPUSEL/PBxSEL registers have taken effect. (A zero-to-one transition on SR.CKRDY is detected). • CFD - Clock Failure Detected: – The system detects that the main clock is not running. The Interrupt Status Register contains one bit for each interrupt source.
ATUC64/128/256L3/4U 13.7 User Interface Table 13-7.
ATUC64/128/256L3/4U 13.7.1 Main Clock Control Name: MCCTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - MCSEL • MCSEL: Main Clock Select Table 13-8. Note: Main clocks in ATUC64/128/256L3/4U.
ATUC64/128/256L3/4U 13.7.2 CPU Clock Select Name: CPUSEL Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CPUDIV - - - - CPUSEL • CPUDIV, CPUSEL: CPU Division and Clock Select CPUDIV = 0: CPU clock equals main clock. CPUDIV = 1: CPU clock equals main clock divided by 2(CPUSEL+1).
ATUC64/128/256L3/4U 13.7.3 HSB Clock Select Name: HSBSEL Access Type: Read Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 HSBDIV - - - - HSBSEL This register is read-only and its content is always equal to CPUSEL.
ATUC64/128/256L3/4U 13.7.4 PBx Clock Select Name: PBxSEL Access Type: Read/Write Offset: 0x00C-0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PBDIV - - - - PBSEL • PBDIV, PBSEL: PBx Division and Clock Select PBDIV = 0: PBx clock equals main clock. PBDIV = 1: PBx clock equals main clock divided by 2(PBSEL+1).
ATUC64/128/256L3/4U 13.7.5 Clock Mask Name: CPUMASK/HSBMASK/PBAMASK/PBBMASK Access Type: Read/Write Offset: 0x020-0x02C Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 MASK[31:24] 23 22 21 20 MASK[23:16] 15 14 13 12 MASK[15:8] 7 6 5 4 MASK[7:0] • MASK: Clock Mask If bit n is cleared, the clock for module n is stopped. If bit n is set, the clock for module n is enabled according to the current power mode.
ATUC64/128/256L3/4U Table 13-9. Maskable Module Clocks in ATUC64/128/256L3/4U. Bit CPUMASK HSBMASK PBAMASK PBBMASK 12 - - USART3 - 13 - - SPI - 14 - - TWIM0 - 15 - - TWIM1 - 16 SYSTIMER - TWIS0 - 17 - - TWIS1 - 18 - - PWMA - 19 - - TC0 - 20 - - TC1 - 21 - - ADCIFB - 22 - - ACIFB - 23 - - CAT - 24 - - GLOC - 25 - - AW - 26 - - ABDACB - 27 - - IISC - 31:28 - - - - Note that this register is protected by a lock.
ATUC64/128/256L3/4U 13.7.6 PBA Divided Mask Name: PBADIVMASK Access Type: Read/Write Offset: 0x040 Reset Value: 0x0000007F 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - MASK[6:0] • MASK: Clock Mask If bit n is written to zero, the clock divided by 2(n+1) is stopped.
ATUC64/128/256L3/4U 13.7.7 Clock Failure Detector Control Register Name: CFDCTRL Access Type: Read/Write Offset: 0x054 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CFDEN • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
ATUC64/128/256L3/4U 13.7.8 Unlock Register Name: UNLOCK Access Type: Write-only Offset: 0x058 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
ATUC64/128/256L3/4U 13.7.9 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x0C0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 13.7.10 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x0C4 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 13.7.11 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x0C8 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 13.7.12 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x0CC Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
ATUC64/128/256L3/4U 13.7.13 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x0D0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in ISR.
ATUC64/128/256L3/4U 13.7.14 Status Register Name: SR Access Type: Read-only Offset: 0x0D4 Reset Value: 0x00000020 31 30 29 28 27 26 25 24 AE - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - CKRDY - - - - CFD • AE: Access Error 0: No access error has occurred. 1: A write to lock protected register without unlocking it has occurred.
ATUC64/128/256L3/4U 13.7.15 Peripheral Power Control Register Name: PPCR Access Type: Read/Write Offset: 0x004 Reset Value: 0x000001FA 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PPC[31:24] 23 22 21 20 PPC[23:16] 15 14 13 12 PPC[15:8] 7 6 5 4 PPC[7:0] Table 13-11.
ATUC64/128/256L3/4U • CATRCMASK: CAT Request Clock Mask 0: CAT Request Clock is disabled 1: CAT Request Clock is enabled • ACIFBRCMASK: ACIFB Request Clock Mask 0: ACIFB Request Clock is disabled 1: ACIFB Request Clock is enabled • ADCIFBRCMASK: ADCIFB Request Clock Mask 0: ADCIFB Request Clock is disabled 1: ADCIFB Request Clock is enabled • ASTRCMASK: AST Request Clock Mask 0: AST Request Clock is disabled 1: AST Request Clock is enabled • TWIS0RCMASK: TWIS0 Request Clock Mask 0: TWIS0 Request Clock is di
ATUC64/128/256L3/4U 13.7.16 Reset Cause Register Name: RCAUSE Access Type: Read-only Offset: 0x180 Reset Value: Latest Reset Source 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - AWIRE - JTAG OCDRST 7 6 5 4 3 2 1 0 - SLEEP - - WDT EXT BOD POR • AWIRE: aWire Reset This bit is set when the last reset was caused by the aWire.
ATUC64/128/256L3/4U 13.7.17 Wake Cause Register Name: WCAUSE Access Type: Read-only Offset: 0x184 Reset Value: Latest Wake Source 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 WCAUSE[31:24] 23 22 21 20 19 WCAUSE[23:16] 15 14 13 12 11 WCAUSE[15:8] 7 6 5 4 3 WCAUSE[7:0] A bit in this register is set on wake up caused by the peripheral referred to in Table 13-12 on page 239. Table 13-12.
ATUC64/128/256L3/4U 13.7.18 Asynchronous Wake Up Enable Register Name: AWEN Access Type: Read/Write Offset: 0x188 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 AWEN[31:24] 23 22 21 20 AWEN[23:16] 15 14 13 12 AWEN[15:8] 7 6 5 4 AWEN[7:0] Each bit in this register corresponds to an asynchronous wake-up source, according to Table 13-13 on page 240. 0: The corresponding wake up is disabled.
ATUC64/128/256L3/4U 13.7.19 Configuration Register Name: CONFIG Access Type: Read-Only Offset: 0x3F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 HSBPEVC - - - PBD PBC PBB PBA This register shows the configuration of the PM. • HSBPEVC:HSB PEVC Clock Implemented 0: HSBPEVC not implemented. 1: HSBPEVC implemented.
ATUC64/128/256L3/4U 13.7.20 Version Register Name: VERSION Access Type: Read-Only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 13.8 Module Configuration The specific configuration for each PM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the “Synchronous Clocks”, “Peripheral Clock Masking” and “Sleep Modes” sections for details. Table 13-14. Power Manager Clocks Clock Name Description CLK_PM Clock for the PM bus interface Table 13-15. Register Reset Values Register Reset Value VERSION 0x00000420 Table 13-16.
ATUC64/128/256L3/4U 14. System Control Interface (SCIF) Rev: 1.1.0.0 14.1 Features • • • • • • • • • • • • • • • 14.2 Supports crystal oscillator 0.
ATUC64/128/256L3/4U 14.4.1 I/O Lines The SCIF provides a number of generic clock outputs, which can be connected to output pins, multiplexed with GPIO lines. The programmer must first program the GPIO controller to assign these pins to their peripheral function. If the I/O pins of the SCIF are not used by the application, they can be used for other purposes by the GPIO controller. Oscillator pins are also multiplexed with GPIO.
ATUC64/128/256L3/4U abled in certain sleep modes to reduce power consumption, as described in the Power Manager chapter. After a hard reset, or when waking up from a sleep mode where the oscillators were disabled, the oscillator will need a certain amount of time to stabilize on the correct frequency. This startup time can be set in the OSCCTRLn register. The SCIF masks the oscillator outputs during the start-up time, to ensure that no unstable clocks propagate to the digital logic.
ATUC64/128/256L3/4U used in Shutdown mode, PINSEL must be written to one, and XIN32_2 and XOUT32_2 must be used. 14.5.3 PLL Operation Rev: 1.1.0.0 The device contains one Phase Locked Loop (PLL), which is controlled by the Phase Locked Loop Interface (PLLIF). The PLL is disabled by default, but can be enabled to provide high frequency source clocks for synchronous or generic clocks.
ATUC64/128/256L3/4U Factor (PLLDIV) fields must be written with the multiplication and division factors, respectively. The PLLMUL must always be greater than 1, creating the PLL frequency: fvco = (PLLMUL+1)/PLLDIV • fREF, if PLLDIV >0 fvco = 2•(PLLMUL+1) • fREF, if PLLDIV = 0 The PLL Options (PLLOPT) field should be configured to proper values according to the PLL operating frequency.
ATUC64/128/256L3/4U Figure 14-2. DFLLIF Block Diagram COARSE 8 DFLL CLK_DFLL FINE 9 8+9 32 CSTEP FSTEP IMUL FMUL FREQUENCY TUNER CLK_DFLLIF_DITHER CLK_DFLLIF_REF DFLLLOCKF DFLLLOCKLOSTF DFLLLOCKC DFLLLOCKA DFLLLOCKLOSTC DFLLLOCKLOSTA 14.5.4.1 Enabling the DFLL The DFLL is enabled by writing a one to the Enable bit (EN) in the DFLLn Configuration Register (DFLLnCONF). No other bits or fields in DFLLnCONF must be changed simultaneously, or before the DFLL is enabled. 14.5.4.
ATUC64/128/256L3/4U FINE, be aware that the output frequency must not exceed the maximum frequency of the device after the division in the clock generator. It is possible to change the value of COARSE and FINE, and thereby the output frequency of the DFLL, while the DFLL is enabled and in use. The DFLL clock is ready to be used when PCLKSR.DFLLnRDY is cleared after enabling the DFLL.
ATUC64/128/256L3/4U only be executed if the Dithering Enable bit (DITHER) in DFLLnCONF has been written to a one. If DITHER is written to a zero DFLLnLOCKA will never occur. If dithering is enabled, the frequency of the dithering is decided by a generic clock (CLK_DFLLIF_DITHER). This clock has to be set up correctly before enabling dithering. Please refer to the Generic Clocks section for details. Figure 14-3.
ATUC64/128/256L3/4U Drift compensation The frequency tuner will automatically compensate for drift in the fDFLL without losing either of the locks. If the FINE value overflows or underflows, which should normally not happen, but could occur due to large drift in temperature and voltage, all locks will be lost, and the COARSE and FINE values will be recalibrated as described earlier.
ATUC64/128/256L3/4U DFLLIF can provide a clock with the energy spread in the frequency domain. This is done by adding or subtracting values from the FINE value. SSG is enabled by writing a one to the Enable bit (EN) in the DFLLn Spread Spectrum Generator Control Register (DFLLnSSG). A generic clock sets the rate at which the SSG changes the frequency of the DFLL clock to generate a spread spectrum (CLK_DFLLIF_DITHER). This is the same clock used by the dithering mechanism.
ATUC64/128/256L3/4U • FINE resolution: The frequency step between two FINE values. This is relatively smaller for high output frequencies. • Resolution of the measurement: If the resolution of the measured fDFLL is low, i.e. the ratio between CLK_DFLL frequency and CLK_DFLLIF_REF is small, then the DFLLIF might lock at a frequency that is lower than the targeted frequency. It is recommended to use a reference clock frequency of 32 KHz or lower to avoid this issue for low target frequencies.
ATUC64/128/256L3/4U The CTRL, HYST, and LEVEL fields in the BOD Control Register are loaded factory defined calibration values from flash fuses after a reset. If the Flash Calibration Done bit in the BOD Control Register (BOD.FCD) is zero, the flash calibration will be redone after any reset, and the BOD.FCD bit will be set before program execution starts in the CPU. If BOD.FCD is one, the flash calibration is redone after any reset except for a BOD reset. The BOD.
ATUC64/128/256L3/4U 14.5.7 System RC Oscillator (RCSYS) Rev: 1.1.1.0 The system RC oscillator has a startup time of three cycles, and is always available except in some sleep modes. Please refer to the Power Manager chapter for details. The system RC oscillator operates at a nominal frequency of 115kHz, and is calibrated using the Calibration Value field (CALIB) in the RC Oscillator Calibration Register (RCCR). After a Power-on Reset (POR), the RCCR.
ATUC64/128/256L3/4U 14.5.8.3 Factory calibration After a Power-on Reset (POR) the VREGCR.CALIB field is loaded with a factory defined calibration value. This value is chosen so that the normal output voltage of the regulator after a powerup is 1.8V. Although it is not recommended to override default factory settings, it is still possible to override these default values by writing to VREGCR.CALIB. If the Flash Calibration Done bit in VREGCR (VREGCR.
ATUC64/128/256L3/4U synchronisation, the masking is not immediately effective, so software should wait for the VREGCR.POR18MASK to read as one before assuming the masking is effective. The output of the POR18 detector is zero if the VDDCORE voltage is below the POR18 poweron threshold level, and one if the VDDCORE voltage is above the POR18 power-on threshold level. The output of the POR18 detector (before masking) can be read from the POR18 Value bit (VREGCR.POR18VALUE). 14.5.9 3.
ATUC64/128/256L3/4U Supply Monitor 3.3V Detection bit in the Interrupt Mask Register (IMR.SM33DET) is set. This bit is set by writing a one to the corresponding bit in the Interrupt Enable Register (IER.SM33DET). If SM33.CTRL is one, a POR will be generated when the voltage drops below the threshold. If SM33.CTRL is two, the device will not be reset. 14.5.9.4 Factory calibration After a reset the SM33.CALIB field is loaded with a factory defined value.
ATUC64/128/256L3/4U the BRIFARDY bit in the Interrupt Mask Register (IMR.BRIFARDY) is set. This bit is set by writing a one to the corresponding bit in the Interrupt Enable Register (IER.BRIFARDY). After powering up the device the Backup Register Interface Valid bit in PCLKSR (PCLKSR.BRIFAVALID) is cleared, indicating that the content of the backup registers has not been written and contains the reset value. After writing to one of the backup registers the PCLKSR.BRIFAVALID bit is set.
ATUC64/128/256L3/4U Figure 14-7. High Resolution Prescaler Generation CKSEL Divider Mask HRCOUNT HRPEN HRPCLK The HRP is enabled by writing a one to the High Resolution Prescaler Enable (HRPEN) bit in the High Resolution Prescaler Control Register (HRPCR). The user can select a clock source for the HRP by writing to the Clock Selection (CKSEL) field of the HRPCR register.
ATUC64/128/256L3/4U The user must configure the FP frequency by writing to the FPMUL and FPDIV fields of the FPMUL and FPDIV registers. FPMUL and FPDIV must not be equal to zero and FPDIV must be greater or equal to FPMUL. This results in the output frequency: fFPCLK = fSRC * FPMUL/ (2*FPDIV) The CKSEL field can not be changed dynamically but the FPMUL and FPDIV fields can be changed on-the-fly.
ATUC64/128/256L3/4U Figure 14-10. Generic Clock Generation S leep C ontroller G eneric C lock S ources f G C LK 0 fS R C M ask D ivider OSCSEL 14.5.15.1 1 D IV E N D IV G eneric C lock CEN Enabling a generic clock A generic clock is enabled by writing a one to the Clock Enable bit (CEN) in the Generic Clock Control Register (GCCTRL). Each generic clock can individually select a clock source by writing to the Oscillator Select field (OSCSEL).
ATUC64/128/256L3/4U • PLLLOCK - PLL Lock – A 0 to 1 transition on the PCLKSR.PLLLOCK bit is detected. • PLLLOCKLOST - PLL Lock Lost – A to 1 transition on the PCLKSR.PLLLOCKLOST bit is detected. • BRIFARDY - Backup Register Interface Ready. – A 0 to 1 transition on the PCLKSR.BRIFARDY bit is detected. • DFLL0RCS - DFLL Reference Clock Stopped: – A 0 to 1 transition on the PCLKSR.DFLLRCS bit is detected. • DFLL0RDY - DFLL Ready: – A 0 to 1 transition on the PCLKSR.DFLLRDY bit is detected.
ATUC64/128/256L3/4U 14.6 User Interface Table 14-2.
ATUC64/128/256L3/4U Table 14-2.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U 14.6.
ATUC64/128/256L3/4U • DFLL0LOCKLOSTC: DFLL0 Lock Lost on Coarse Value 0: DFLL has not lost its Coarse lock or has never been enabled. 1: DFLL has lost its Coarse lock, either by disabling the DFLL or due to faulty operation. • DFLL0LOCKA: DFLL0 Locked on Accurate Value 0: DFLL is unlocked on Accurate value. 1: DFLL is locked on Accurate value, and is ready to be selected as clock source with an accurate output clock. • DFLL0LOCKF: DFLL0 Locked on Fine Value 0: DFLL is unlocked on Fine value.
ATUC64/128/256L3/4U 14.6.7 Unlock Register Name: UNLOCK Access Type: Write-only Offset: 0x0018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 ADDR[9:8] 1 0 ADDR[7:0] To unlock a write protected register, first write to the UNLOCK register with the address of the register to unlock in the ADDR field and 0xAA in the KEY field.
ATUC64/128/256L3/4U 14.6.8 Oscillator Control Register Name: OSCCTRLn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - OSCEN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 1 0 - - - - AGC STARTUP[3:0] 2 GAIN[1:0] MODE • OSCEN: Oscillator Enable 0: The oscillator is disabled. 1: The oscillator is enabled.
ATUC64/128/256L3/4U 14.6.9 32KHz Oscillator Control Register Name: OSCCTRL32 Access Type: Read/Write Reset Value: 0x00000004 31 30 29 28 27 26 25 24 RESERVED - - - - - - - 23 22 21 20 19 18 17 16 - - - - - 15 14 13 12 11 - - - - - 7 6 5 4 3 2 1 0 - - - - EN1K EN32K PINSEL OSC32EN STARTUP[2:0] 10 9 8 MODE[2:0] Note: This register is only reset by Power-On Reset • RESERVED This bit must always be written to zero.
ATUC64/128/256L3/4U • MODE: Oscillator Mode Table 14-4. MODE Operation Mode for 32 KHz Oscillator Description 0 External clock connected to XIN32, XOUT32 can be used as general-purpose I/O (no crystal) 1 Crystal mode. Crystal is connected to XIN32/XOUT32. 2 Reserved 3 Reserved 4 Crystal and high current mode. Crystal is connected to XIN32/XOUT32. 5 Reserved 6 Reserved 7 Reserved • EN1K: 1 KHz output Enable 0: The 1 KHz output is disabled. 1: The 1 KHz output is enabled.
ATUC64/128/256L3/4U 14.6.10 DFLLn Configuration Register Name: DFLLnCONF Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 COARSE[7:0] 23 22 21 20 19 18 17 16 - - - - - - - FINE[8] 15 14 13 12 11 10 9 8 FINE[7:0] 7 6 5 4 3 2 1 0 - QLEN CCEN - LLAW DITHER MODE EN • COARSE: Coarse Calibration Value Set the value of the coarse calibration register. If in closed loop mode, this field is Read-only.
ATUC64/128/256L3/4U 14.6.11 DFLLn Multiplier Register Name: DFLLnMUL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 IMUL[15:8] 23 22 21 20 IMUL[7:0] 15 14 13 12 FMUL[15:8] 7 6 5 4 FMUL[7:0] • IMUL: Integer Multiply Factor This field, together with FMUL, determines the ratio between fDFLL and fREFthe DFLL. IMUL is the integer part, while the FMUL is the fractional part.
ATUC64/128/256L3/4U 14.6.12 DFLLn Maximum Step Register Name: DFLLnSTEP Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - FSTEP[8] 23 22 21 20 19 18 17 16 FSTEP[7:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CSTEP[7:0] • FSTEP: Fine Maximum Step This indicates the maximum step size during fine adjustment in closed-loop mode.
ATUC64/128/256L3/4U 14.6.13 DFLLn Spread Spectrum Generator Control Register Name: DFLLnSSG Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 9 8 - - - 7 6 5 4 3 2 1 0 - - - - - - PRBS EN STEPSIZE[4:0] 12 11 10 AMPLITUDE[4:0] • STEPSIZE: SSG Step Size Sets the step size of the spread spectrum. • AMPLITUDE: SSG Amplitude Sets the amplitude of the spread spectrum.
ATUC64/128/256L3/4U 14.6.14 DFLLn Ratio Register Name: DFLLnRATIO Access Type: Read-only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 RATIODIFF[15:8] 23 22 21 20 19 RATIODIFF[7:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - NUMREF[4:0] • RATIODIFF: Multiplication Ratio Difference In closed-loop mode, this field indicates the error in the ratio between the VCO frequency and the target frequency.
ATUC64/128/256L3/4U 14.6.15 DFLLn Synchronization Register Name: DFLLnSYNC Access Type: Write-only Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchronization To be able to read the current value of DFLLnCONF or DFLLnRATIO in closed-loop mode, this bit should be written to one.
ATUC64/128/256L3/4U 14.6.16 BOD Control Register Name: BOD Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 SFV - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 - HYST CTRL 1 0 LEVEL • SFV: Store Final Value 0: The register is read/write 1: The register is read-only, to protect against further accidental writes.
ATUC64/128/256L3/4U Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
ATUC64/128/256L3/4U 14.6.17 Voltage Regulator Calibration Register Name: VREGCR Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 SFV INTPD - - - DBG- POR18VALUE POR33VALUE 23 22 21 20 19 18 17 16 POR18MASK POR18STAT US POR18EN POR33MASK POR33STAT US POR33EN DEEPDIS FCD 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 3 1 0 ON VREGOK EN - - CALIB 2 SELVDD • SFV: Store Final Value 0: The register is read/write.
ATUC64/128/256L3/4U 1: Power-on Reset 3.3V is masked. • POR33STATUS: Power-on Reset 3.3V Status 0: Power-on Reset is disabled. 1: Power-on Reset is enabled. This bit is read-only. Writing to this bit has no effect. • POR33EN: Power-on Reset 3.3V Enable 0: Writing a zero to this bit disables the POR33 detector. 1: Writing a one to this bit enables the POR33 detector. • DEEPDIS: Disable Regulator Deep Mode 0: Regulator will enter deep mode in low-power sleep modes for lower power consumption.
ATUC64/128/256L3/4U 14.6.18 System RC Oscillator Calibration Register Name: RCCR Access Type: Read/Write Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - FCD 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 CALIB[9:8] 1 0 CALIB[7:0] • FCD: Flash Calibration Done 0: The flash calibration will be redone after any reset. 1: The flash calibration will only be redone after a Power-on Reset.
ATUC64/128/256L3/4U 14.6.19 Supply Monitor 33 Calibration Register Name: SM33 Access Type: Read/Write Reset Value: - 31 30 29 28 27 - - - - 23 22 21 20 19 - - - - 15 14 13 12 - - - - 7 6 5 4 FS - - - 26 25 24 18 17 16 - ONSM SFV FCD 11 10 9 8 1 0 SAMPFREQ CALIB 3 2 CTRL • SAMPFREQ: Sampling Frequency Selects the sampling mode frequency of the 3.3V supply monitor.
ATUC64/128/256L3/4U Selects the operating mode for the SM33. Table 14-6. CTRL Operation Mode for SM33 Description 0 SM33 is disabled. 1 SM33 is enabled and can reset the device. An interrupt request will be generated if the corresponding interrupt is enabled in the IMR register. 2 SM33 is enabled and cannot reset the device. An interrupt request will be generated if the corresponding interrupt is enabled in the IMR register.
ATUC64/128/256L3/4U 14.6.20 Temperature Sensor Configuration Register Name: TSENS Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - EN • EN: Temperature Sensor Enable 0: The Temperature Sensor is disabled. 1: The Temperature Sensor is enabled. Note that this register is protected by a lock.
ATUC64/128/256L3/4U 14.6.21 Name: 120MHz RC Oscillator Configuration Register RC120MCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • EN: RC120M Enable 0: The 120 MHz RC oscillator is disabled. 1: The 120 MHz RC oscillator is enabled. Note that this register is protected by a lock.
ATUC64/128/256L3/4U 14.6.22 Backup Register n Name: BRn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] This is a set of general-purpose read/write registers. Data stored in these registers is retained when the device is in Shutdown. Before writing to these registers the user must ensure that PCLKSR.BRIFARDY is not set.
ATUC64/128/256L3/4U 14.6.23 32kHz RC Oscillator Configuration Register Name: RC32KCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - EN • EN: RC32K Enable 0: The 32 kHz RC oscillator is disabled. 1: The 32 kHz RC oscillator is enabled. Note that this register is protected by a lock.
ATUC64/128/256L3/4U 14.6.24 Generic Clock Control Name: GCCTRL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 - - - 7 6 5 4 3 2 1 0 - - - - - - DIVEN CEN OSCSEL[4:0] There is one GCCTRL register per generic clock in the design.
ATUC64/128/256L3/4U 14.6.25 Name: PLL Control Register PLLn Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 - - 23 22 21 20 - - - - 15 14 13 12 - - - - 7 6 5 4 - - 27 26 25 24 18 17 16 9 8 1 0 PLLCOUNT PLLOPT 19 PLLMUL 11 10 PLLDIV 3 2 PLLOSC PLLEN • PLLCOUNT: PLL Count Specifies the number of RCSYS clock cycles before ISR.
ATUC64/128/256L3/4U • PLLEN: PLL Enable 0: PLL is disabled. 1: PLL is enabled. Note that it is not possible to change any of the PLL configuration bits when the PLL is enabled, Any write to PLLn while the PLL is enabled will be discarded. Note that this register is protected by a lock. To write to this register the UNLOCK register has to be written first. Please refer to the UNLOCK register description for details.
ATUC64/128/256L3/4U 14.6.26 High Resolution Prescaler Control Register Name: HRPCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 10 9 8 2 1 0 HRCOUNT[23:16] 23 22 21 20 19 HRCOUNT[15:8] 15 14 13 12 11 HRCOUNT[7:0] 7 6 5 4 - - - - 3 CKSEL HRPEN • HRCOUNT: High Resolution Counter Specify the input clock period to count to generate the output clock edge.
ATUC64/128/256L3/4U 14.6.27 Fractional Prescaler Control Register Name: FPCR Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - CKSEL FPEN • CKSEL: Clock input selection This field selects the Clock input for the prescaler.
ATUC64/128/256L3/4U 14.6.28 Fractional Prescaler Mul Register Name: FPMUL Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 FPMUL[15:8] 7 6 5 4 FPMUL[7:0] • FPMUL: Fractional Prescaler Multiplication Factor This field selects the multiplication factor for the prescaler. Notice that FPMUL is always smaller than FPDIV.
ATUC64/128/256L3/4U 14.6.29 Fractional Prescaler Div Register Name: FPDIV Access Type: Read/Write Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 FPDIV[15:8] 7 6 5 4 FPDIV[7:0] • FPDIV: Fractional Prescaler Division Factor This field selects the division factor for the prescaler. Notice that FPMUL must be smaller than FPDIV.
ATUC64/128/256L3/4U 14.6.30 Commonly used Modules Version Register Name: CMVERSION Access Type: Read-only Offset: 0x03BC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.31 GCLK Prescaler Version Register Name: GCLKPRESCVERSION Access Type: Read-only Offset: 0x03C0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.32 PLL Version Register Name: PLLVERSION Access Type: Read-only Offset: 0x03C4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.33 Oscillator 0 Version Register Name: OSC0VERSION Access Type: Read-only Offset: 0x03C8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.34 32KHz Oscillator Version Register Name: OSC32VERSION Access Type: Read-only Offset: 0x03CC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.35 Digital Frequency Locked Loop Version Register Name: DFLLIF VERSION Access Type: Read-only Offset: 0x03D0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.36 Brown-Out Detector Version Register Name: BODIFAVERSION Access Type: Read-only Offset: 0x03D4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.37 Voltage Regulator Version Register Name: VREGIFBVERSION Access Type: Read-only Offset: 0x03D8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.38 RC Oscillator Version Register Name: RCOSCIFAVERSION Access Type: Read-only Offset: 0x03DC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.39 3.3V Supply Monitor Version Register Name: SM33IFAVERSION Access Type: Read-only Offset: 0x03E0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.40 Temperature Sensor Version Register Name: TSENSIFAVERSION Access Type: Read-only Offset: 0x03E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.41 120MHz RC Oscillator Version Register Name: RC120MIFAVERSION Access Type: Read-only Offset: 0x03EC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.42 Backup Register Interface Version Register Name: BRIFAVERSION Access Type: Read-only Offset: 0x03F0 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.43 32kHz RC Oscillator Version Register Name: RC32KIFAVERSION Access Type: Read-only Offset: 0x03F4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.44 Generic Clock Version Register Name: GCLKVERSION Access Type: Read-only Offset: 0x03F8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.6.45 SCIF Version Register Name: VERSION Access Type: Read-only Offset: 0x03FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:0] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 14.7 Module Configuration The specific configuration for each SCIF instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 14-7. MODULE Clock Name Module Name Clock Name Description SCIF CLK_SCIF Clock for the SCIF bus interface Table 14-8.
ATUC64/128/256L3/4U In ATUC64/128/256L3/4U, there are 10 generic clocks. These are allocated to different functions as shown in Table 14-10. Table 14-10.
ATUC64/128/256L3/4U . Table 14-12. PLL Clock Sources PLLOSC Clock/Oscillator Description 0 OSC0 Output clock from Oscillator0 1 GCLK8 Generic clock 8 2-3 Reserved Table 14-13. Generic Clock number of DIV bits Generic Clock Number of DIV bits 0 8 1 8 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 16 Table 14-14.
ATUC64/128/256L3/4U Table 14-14.
ATUC64/128/256L3/4U 15. Asynchronous Timer (AST) Rev: 3.1.0.1 15.1 Features • 32-bit counter with 32-bit prescaler • Clocked Source • • • • • 15.
ATUC64/128/256L3/4U 15.3 Block Diagram Figure 15-1. Asynchronous Timer Block Diagram CLK_AST CONTROL REGISTER CLK_AST CLK_AST CSSEL WAKE ENABLE REGISTER Wake Control COUNTER VALUE Wake EN PSEL OSC32 RCSYS PB clock 32-bit Prescaler CLK_AST_PRSC CLK_AST_CNT 32-bit Counter OVF GCLK others DIGITAL TUNER REGISTER 15.
ATUC64/128/256L3/4U • Generic clock (GCLK). One of the generic clocks is connected to the AST. This clock must be enabled before use, and remains enabled in sleep modes when the PB clock is active. • 1KHz clock from the 32KHz oscillator (CLK_1K). This clock is only available in crystal mode, and must be enabled before use. In Shutdown mode only the 32 KHz oscillator and the 1KHz clock are available, using certain pins. Please refer to the Power Manager chapter for details. 15.4.
ATUC64/128/256L3/4U 15.5.1.2 Changing the source clock The CLK_AST_PRSC must be disabled before switching to another source clock. The Clock Busy bit in the Status Register (SR.CLKBUSY) indicates whether the clock is busy or not. This bit is set when the CEN bit in the CLOCK register is changed, and cleared when the CLOCK register can be changed. To change the clock: • Write a zero to CLOCK.CEN to disable the clock, without changing CLOCK.CSSEL • Wait until SR.
ATUC64/128/256L3/4U 15.5.2.3 Calendar operation When the CAL bit in the Control Register is one, the counter operates in calendar mode. Before this mode is enabled, the prescaler should be set up to give a pulse every second. The date and time can then be read from or written to the Calendar Value (CALV) register. Time is reported as seconds, minutes, and hours according to the 24-hour clock format. Date is the numeral date of month (starting on 1).
ATUC64/128/256L3/4U prescaler when the AST is enabled. The bit is selected by the Interval Select field in the corresponding Periodic Interval Register (PIRn.INSEL), resulting in a periodic interrupt frequency of f CS f PA = -----------------------INSEL + 1 2 where fCS is the frequency of the selected clock source. The corresponding PERn bit in the Status Register (SR) will be set when the selected bit in the prescaler has a 0-to-1 transition.
ATUC64/128/256L3/4U The peripheral event will be generated if the corresponding bit in the Event Mask (EVM) register is set. Bits in EVM register are set by writing a one to the corresponding bit in the Event Enable (EVE) register, and cleared by writing a one to the corresponding bit in the Event Disable (EVD) register. 15.5.5 AST wakeup The AST can wake up the CPU directly, without the need to trigger an interrupt.
ATUC64/128/256L3/4U If ADD is ‘1’, the prescaler frequency is increased: 1 f TUNED = f 0 1 + -------------------------------------------------------------------------------- 256 roundup -------------------- 2 EXP – 1 VALUE Note that for these formulas to be within an error of 0.01%, it is recommended that the prescaler bit that is used as the clock for the counter (selected by CR.PSEL) or to trigger the periodic interrupt (selected by PIRn.INSEL) be bit 6 or higher. 15.5.
ATUC64/128/256L3/4U 15.6 User Interface Table 15-1.
ATUC64/128/256L3/4U 15.6.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 12 11 10 9 8 - - - - - - CA1 CA0 7 6 5 4 3 2 1 0 - - - - - CAL PCLR EN PSEL When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.2 Name: Counter Value CV Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set, writes to this register will be discarded and this register will read as zero. • VALUE: AST Value The current value of the AST counter.
ATUC64/128/256L3/4U 15.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY CLKBUSY - - READY BUSY 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF • CLKRDY: Clock Ready This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when the SR.
ATUC64/128/256L3/4U 15.6.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set, writes to this register will be discarded. Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 15.6.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 15.6.6 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 15.6.7 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - CLKRDY - - - READY - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 15.6.8 Name: Wake Enable Register WER Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.9 Name: Alarm Register 0 AR0 Access Type: Read/Write Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
ATUC64/128/256L3/4U 15.6.10 Name: Alarm Register 1 AR1 Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 18 17 16 11 10 9 8 3 2 1 0 VALUE[31:24] 23 22 21 20 19 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: Alarm Value When the counter reaches this value, an alarm is generated.
ATUC64/128/256L3/4U 15.6.11 Name: Periodic Interval Register 0 PIR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.12 Name: Periodic Interval Register 1 PIR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - INSEL When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.13 Name: Clock Control Register CLOCK Access Type: Read/Write Offset: 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CEN CSSEL When writing to this register, follow the sequence in Section 15.5.1 on page 324.
ATUC64/128/256L3/4U 15.6.14 Name: Digital Tuner Register DTR Access Type: Read/Write Offset: 0x44 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 VALUE 7 6 5 - - ADD 4 EXP When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • VALUE: 0: The frequency is unchanged.
ATUC64/128/256L3/4U 15.6.15 Name: Event Enable Register EVE Access Type: Write-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.16 Name: Event Disable Register EVD Access Type: Write-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero.
ATUC64/128/256L3/4U 15.6.17 Name: Event Mask Register EVM Access Type: Read-only Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - PER1 PER0 15 14 13 12 11 10 9 8 - - - - - - ALARM1 ALARM0 7 6 5 4 3 2 1 0 - - - - - - - OVF 0: The corresponding peripheral event is disabled. 1: The corresponding peripheral event is enabled.
ATUC64/128/256L3/4U 15.6.18 Name: Calendar Value CALV Access Type: Read/Write Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 YEAR 23 22 21 MONTH[3:2] 20 MONTH[1:0] 15 19 18 17 DAY 14 13 12 6 16 HOUR[4] 11 10 HOUR[3:0] 7 24 9 8 1 0 MIN[5:2] 5 4 3 MIN[1:0] 2 SEC When the SR.BUSY bit is set writes to this register will be discarded and this register will read as zero. • YEAR: Year Current year. The year is considered a leap year if YEAR[1:0] = 0.
ATUC64/128/256L3/4U 15.6.19 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF0 Reset Value: - 31 30 29 - - - 23 22 21 - - - 15 14 13 12 11 10 PIR1WA PIR0WA - NUMPIR - - 7 6 5 4 3 2 - • • • • • • • 28 27 26 25 24 17 16 9 8 PER1VALUE 20 19 18 PER0VALUE DTEXPVALUE NUMAR 1 0 DTEXPWA DT This register gives the configuration used in the specific device. Also refer to the Module Configuration section.
ATUC64/128/256L3/4U 15.6.20 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 15.7 Module Configuration The specific configuration for each AST instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 15-3. AST Configuration Feature AST Number of alarm comparators 1 Number of periodic comparators 1 Digital tuner On Table 15-4.
ATUC64/128/256L3/4U 16. Watchdog Timer (WDT) Rev: 4.1.0.0 16.1 Features • • • • • 16.2 Watchdog Timer counter with 32-bit counter Timing window watchdog Clocked from system RC oscillator or the 32 KHz crystal oscillator Configuration lock WDT may be enabled at reset by a fuse Overview The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the software. This allows the device to recover from a condition that has caused the system to be unstable.
ATUC64/128/256L3/4U 16.4.1 Power Management When the WDT is enabled, the WDT remains clocked in all sleep modes. It is not possible to enter sleep modes where the source clock of CLK_CNT is stopped. Attempting to do so will result in the device entering the lowest sleep mode where the source clock is running, leaving the WDT operational. Please refer to the Power Manager chapter for details about sleep modes.
ATUC64/128/256L3/4U To change the clock for the WDT the following steps need to be taken. Note that the WDT should always be disabled before changing the CLK_CNT source: 1. Write a zero to the Clock Enable (CEN) bit in the CTRL Register, leaving the other bits as they are in the CTRL Register. This will stop CLK_CNT. 2. Read back the CTRL Register until the CEN bit reads zero. The clock has now been stopped. 3.
ATUC64/128/256L3/4U Figure 16-2. Basic Mode WDT Timing Diagram, normal operation. t= t 0 T psel T im e o u t W rite o n e to C L R .W D T C L R W a tc h d o g re s e t If the WDT counter is not cleared within Tpsel a watchdog reset will be issued at the end of Tpsel, see Figure 16-3 on page 355. Figure 16-3. Basic Mode WDT Timing Diagram, no clear within Tpsel. t= t 0 T p se l T im eo u t W rite o n e to C L R .W D T C LR W a tch d og reset 16.5.1.
ATUC64/128/256L3/4U The PSEL and Time Ban Prescale Select (TBAN) fields in the CTRL Register selects the WDT timeout period Ttimeout = Ttban + Tpsel = (2(TBAN+1) + 2(PSEL+1)) / fclk_cnt where Ttban sets the time period when clearing the WDT counter by writing to the CLR.WDTCLR bit is not allowed. Doing so will result in a watchdog reset, the device will receive a reset and the code will start executing form the boot vector, see Figure 16-5 on page 356. The WDT counter will be cleared.
ATUC64/128/256L3/4U 16.5.3 Disabling the WDT The WDT is disabled by writing a zero to the CTRL.EN bit. When disabling the WDT no other bits in the CTRL Register should be changed until the CTRL.EN bit reads back as zero. If the CTRL.CEN bit is written to zero, the CTRL.EN bit will never read back as zero if changing the value from one to zero. 16.5.4 Flash Calibration The WDT can be enabled at reset. This is controlled by the WDTAUTO fuse.
ATUC64/128/256L3/4U 16.6 User Interface Table 16-1. Note: WDT Register Memory Map Offset Register Register Name Access Reset 0x000 Control Register CTRL Read/Write 0x00010080 0x004 Clear Register CLR Write-only 0x00000000 0x008 Status Register SR Read-only 0x00000003 0x3FC Version Register VERSION Read-only -(1) 1. The reset value for this register is device specific. Please refer to the Module Configuration section at the end of this chapter.
ATUC64/128/256L3/4U 16.6.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x000 Reset Value: 0x00010080 31 30 29 28 27 26 25 24 19 18 17 16 CSSEL CEN 9 8 KEY 23 22 21 - 20 TBAN 15 14 13 12 11 10 - - - 7 6 5 4 3 2 1 0 FCD - - - SFV MODE DAR EN PSEL • KEY • • • • • • • This field must be written twice, first with key value 0x55, then 0xAA, for a write operation to be effective. This field always reads as zero.
ATUC64/128/256L3/4U • DAR: WDT Disable After Reset 0: After a watchdog reset, the WDT will still be enabled. 1: After a watchdog reset, the WDT will be disabled. • EN: WDT Enable 0: WDT is disabled. 1: WDT is enabled. After writing to this bit the read back value will not change until the WDT is enabled/disabled. This due to internal synchronization.
ATUC64/128/256L3/4U 16.6.2 Name: Clear Register CLR Access Type: Write-only Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - WDTCLR When the Watchdog Timer is enabled, this Register must be periodically written within the window time frame or within the watchdog timeout period, to prevent a watchdog reset.
ATUC64/128/256L3/4U 16.6.3 Name: Status Register SR Access Type: Read-only Offset: 0x008 Reset Value: 0x00000003 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - CLEARED WINDOW • CLEARED: WDT Counter Cleared This bit is cleared when writing a one to the CLR.WDTCLR bit. This bit is set when clearing the WDT counter is done.
ATUC64/128/256L3/4U 16.6.4 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 16.7 Module Configuration The specific configuration for each WDT instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 16-2. WDT Clocks Clock Name Description CLK_WDT Clock for the WDT bus interface Table 16-3.
ATUC64/128/256L3/4U 17. External Interrupt Controller (EIC) Rev: 3.0.2.0 17.1 Features • • • • • • • 17.2 Dedicated interrupt request for each interrupt Individually maskable interrupts Interrupt on rising or falling edge Interrupt on high or low level Asynchronous interrupts for sleep modes without clock Filtering of interrupt lines Non-Maskable NMI interrupt Overview The External Interrupt Controller (EIC) allows pins to be configured as external interrupts.
ATUC64/128/256L3/4U 17.4 I/O Lines Description Table 17-1. 17.5 I/O Lines Description Pin Name Pin Description Type NMI Non-Maskable Interrupt Input EXTINTn External Interrupt Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 17.5.1 I/O Lines The external interrupt pins (EXTINTn and NMI) may be multiplexed with I/O Controller lines.
ATUC64/128/256L3/4U Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge, or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL registers. Each interrupt has a bit INTn in each of these registers. Writing a zero to the INTn bit in the MODE register enables edge triggered interrupts, while writing a one to the bit enables level triggered interrupts.
ATUC64/128/256L3/4U Figure 17-2. Timing Diagram, Synchronous Interrupts, High Level or Rising Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on Figure 17-3. Timing Diagram, Synchronous Interrupts, Low Level or Falling Edge CLK_SYNC EXTINTn/NMI ISR.INTn: FILTER off ISR.INTn: FILTER on 17.6.3 Non-Maskable Interrupt The NMI supports the same features as the external interrupts, and is accessed through the same registers. The description in Section 17.6.
ATUC64/128/256L3/4U When CLK_SYNC is stopped only asynchronous interrupts remain active, and any short spike on this interrupt will wake up the device. EIC_WAKE will restart CLK_SYNC and ISR will be updated on the first rising edge of CLK_SYNC. Figure 17-4. Timing Diagram, Asynchronous Interrupts CLK_SYNC CLK_SYNC E X T IN T n /N M I 17.6.5 E X T IN T n /N M I IS R .IN T n : r is in g E D G E o r h ig h LEVEL IS R .
ATUC64/128/256L3/4U 17.7 User Interface Table 17-2.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.
ATUC64/128/256L3/4U 17.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 17.8 Module Configuration The specific configuration for each EIC instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 17-3. EIC Configuration Feature EIC Number of external interrupts, including NMI 6 Table 17-4. EIC Clocks Clock Name Description CLK_EIC Clock for the EIC bus interface Table 17-5.
ATUC64/128/256L3/4U 18. Frequency Meter (FREQM) Rev: 3.1.0.1 18.1 Features • • • • 18.2 Accurately measures a clock frequency Selectable reference clock A selectable clock can be measured Ratio can be measured with 24-bit accuracy Overview The Frequency Meter (FREQM) can be used to accurately measure the frequency of a clock by comparing it to a known reference clock. 18.3 Block Diagram Figure 18-1.
ATUC64/128/256L3/4U 18.4.2 Clocks The clock for the FREQM bus interface (CLK_FREQM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the FREQM before disabling the clock, to avoid freezing the FREQM ia an undefined state. A set of clocks can be selected as reference (CLK_REF) and another set of clocks can be selected for measurement (CLK_MSR).
ATUC64/128/256L3/4U • Write a zero to the MODE.REFCEN to disable he clock, without changing the other bits/fields in the Mode register. • Wait until the SR.RCLKBUSY bit reads as zero. 18.5.1.1 18.5.2 Cautionary note Note that if clock selected as source for CLK_REF is stopped during a measurement, this will not be detected by the FREQM. The BUSY bit in the STATUS register will never be cleared, and the DONE interrupt will never be triggered.
ATUC64/128/256L3/4U 18.6 User Interface Table 18-1.
ATUC64/128/256L3/4U 18.6.1 Name: Control Register CTRL Access Type: Write-only Offset: 0x000 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - START • START Writing a zero to this bit has no effect. Writing a one to this bit will start a measurement.
ATUC64/128/256L3/4U 18.6.2 Name: Mode Register MODE Access Type: Read/Write Offset: 0x004 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 REFCEN - - - - - - - 23 22 21 20 19 18 17 16 - - - 15 14 13 CLKSEL 12 11 10 9 8 2 1 0 REFNUM 7 6 5 4 3 - - - - - REFSEL • REFCEN: Reference Clock Enable 0: The reference clock is disabled 1: The reference clock is enabled • CLKSEL: Clock Source Selection Selects the source for CLK_MSR.
ATUC64/128/256L3/4U 18.6.3 Status Register Name: STATUS Access Type: Read-only Offset: 0x008 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKBUSY BUSY • RCLKBUSY: FREQM Reference Clock Status 0: The FREQM ref clk is ready, so a measurement can start.
ATUC64/128/256L3/4U 18.6.4 Value Register Name: VALUE Access Type: Read-only Offset: 0x00C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 3 2 1 0 VALUE[23:16] 15 14 13 12 VALUE[15:8] 7 6 5 4 VALUE[7:0] • VALUE: Result from measurement.
ATUC64/128/256L3/4U 18.6.5 Interrupt Enable Register Name: IER Access Type: Write-only Offset: 0x010 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 18.6.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x014 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 18.6.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x018 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 18.6.8 Interrupt Status Register Name: ISR Access Type: Read-only Offset: 0x01C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE 0: The corresponding interrupt is cleared. 1: The corresponding interrupt is pending.
ATUC64/128/256L3/4U 18.6.9 Interrupt Clear Register Name: ICR Access Type: Write-only Offset: 0x020 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - RCLKRDY DONE Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 18.6.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x3FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 18.7 Module Configuration The specific configuration for each FREQM instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 18-2. FREQM Clock Name Module Name FREQM Table 18-3.
ATUC64/128/256L3/4U Table 18-5.
ATUC64/128/256L3/4U 19. General-Purpose Input/Output Controller (GPIO) Rev: 2.1.3.5 19.1 Features • • • • • • • 19.
ATUC64/128/256L3/4U 19.4 I/O Lines Description Pin Name Description Type GPIOn GPIO pin n Digital 19.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 19.5.1 Power Management If the CPU enters a sleep mode that disables clocks used by the GPIO, the GPIO will stop functioning and resume operation after the system wakes up from sleep mode.
ATUC64/128/256L3/4U 19.6 Functional Description The GPIO controls the I/O pins of the microcontroller. The control logic associated with each pin is shown in the figure below. Figure 19-2. Overview of the GPIO PUER* ODER 1 0 Periph. Func. A Output Pullup 0 Periph.Func. B Periph. Func. C 1 ....
ATUC64/128/256L3/4U 19.6.1 Basic Operation 19.6.1.1 Module Configuration The GPIO user interface registers are organized into ports and each port controls 32 different GPIO pins. Most of the registers supports bit wise access operations such as set, clear and toggle in addition to the standard word access. For details regarding interface registers, refer to Section 19.7. 19.6.1.2 Available Features The GPIO features implemented are device dependent, and not all functions are implemented on all pins.
ATUC64/128/256L3/4U 19.6.2 Advanced Operation 19.6.2.1 Peripheral I/O Pin Control When a GPIO pin is assigned to a peripheral function, i.e. the corresponding bit in GPER is zero, output and output enable is controlled by the selected peripheral pin. In addition the peripheral may control some or all of the other GPIO pin functions listed in Table 19-1, if the peripheral supports those features. All pin features not controlled by the selected peripheral is controlled by the GPIO.
ATUC64/128/256L3/4U Register (IER). The module can be configured to generate an interrupt whenever a pin changes value, or only on rising or falling edges. This is controlled by the Interrupt Mode Registers (IMRn). Interrupts on a pin can be enabled regardless of the GPIO pin being controlled by the GPIO or assigned to a peripheral function. An interrupt can be generated on each GPIO pin. These interrupt generators are further grouped into groups of eight and connected to the interrupt controller.
ATUC64/128/256L3/4U Figure 19-5. Interrupt Timing with Glitch Filter Enabled CLK_GPIO Pin Level IFR 19.6.2.7 CPU Local Bus The CPU Local Bus can be used for application where low latency read and write access to the Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the shared Peripheral Bus (PB).
ATUC64/128/256L3/4U 19.7 User Interface The GPIO controller manages all the GPIO pins on the 32-bit AVR microcontroller. The pins are managed as 32-bit ports that are configurable through a Peripheral Bus (PB) interface. Each port has a set of configuration registers. The overall memory map of the GPIO is shown below. The number of pins and hence the number of ports is product specific. Figure 19-6.
ATUC64/128/256L3/4U ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g. IFR), not all access methods are permitted. Note that for ports with less than 32 bits, the corresponding control registers will have unused bits. This is also the case for features that are not implemented for a specific pin. Writing to an unused bit will have no effect. Reading unused bits will always return 0. 19.7.
ATUC64/128/256L3/4U Table 19-2. GPIO Register Memory Map Offset Register Function Register Name Access 0x02C Peripheral Mux Register 1 Toggle PMR1T Write-only Reset - (1) Config.
ATUC64/128/256L3/4U Table 19-2. GPIO Register Memory Map Offset Register Function Register Name Access Reset Config.
ATUC64/128/256L3/4U 19.7.4 Name: GPIO Enable Register GPER Access: Read/Write, Set, Clear, Toggle Offset: 0x000, 0x004, 0x008, 0x00C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-P31: GPIO Enable 0: A peripheral function controls the corresponding pin.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.9 Name: Output Value Register OVR Access: Read/Write, Set, Clear, Toggle Offset: 0x050, 0x054, 0x058, 0x05C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Output Value 0: The value to be driven on the GPIO pin is 0.
ATUC64/128/256L3/4U 19.7.10 Name: Pin Value Register PVR Access: Read-only Offset: 0x060, 0x064, 0x068, 0x06C Reset Value: Depending on pin states 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Pin Value 0: The GPIO pin is at level zero. 1: The GPIO pin is at level one.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.12 Name: Interrupt Enable Register IER Access: Read/Write, Set, Clear, Toggle Offset: 0x090, 0x094, 0x098, 0x09C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Enable 0: Interrupt is disabled for the corresponding pin.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.
ATUC64/128/256L3/4U 19.7.16 Name: Interrupt Flag Register IFR Access: Read, Clear Offset: 0x0D0, 0x0D8 Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Interrupt Flag 0: No interrupt condition has been detected on the corresponding pin.
ATUC64/128/256L3/4U 19.7.17 Name: Event Enable Register EVER Access: Read/Write, Set, Clear, Toggle Offset: 0x180, 0x184, 0x188, 0x18C Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Event Enable 0: Peripheral Event is disabled for the corresponding pin.
ATUC64/128/256L3/4U 19.7.18 Name: Lock Register LOCK Access: Read/Write, Set, Clear, Toggle Offset: 0x1A0, 0x1A4, 0x1A8, 0x1AC Reset Value: - 31 30 29 28 27 26 25 24 P31 P30 P29 P28 P27 P26 P25 P24 23 22 21 20 19 18 17 16 P23 P22 P21 P20 P19 P18 P17 P16 15 14 13 12 11 10 9 8 P15 P14 P13 P12 P11 P10 P9 P8 7 6 5 4 3 2 1 0 P7 P6 P5 P4 P3 P2 P1 P0 • P0-31: Lock State 0: Pin is unlocked.
ATUC64/128/256L3/4U 19.7.19 Name: Unlock Register UNLOCK Access: Write-only Offset: 0x1E0 Reset Value: - 31 30 29 28 27 26 25 24 KEY 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 - - - - - - 7 6 5 4 3 2 8 OFFSET 1 0 OFFSET • OFFSET: Register Offset This field must be written with the offset value of the LOCK, LOCKC or LOCKT register to unlock. This offset must also include the port offset for the register to unlock.
ATUC64/128/256L3/4U 19.7.20 Name: Access Status Register ASR Access: Read/Write Offset: 0x1E4 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - AE • AE: Access Error This bit is set when a write to a locked register occurs. This bit can be written to 0 by software.
ATUC64/128/256L3/4U 19.7.21 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x1F8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 PARAMETER 23 22 21 20 PARAMETER 15 14 13 12 PARAMETER 7 6 5 4 PARAMETER • PARAMETER: 0: The corresponding pin is not implemented in this GPIO port. 1: The corresponding pin is implemented in this GPIO port. There is one PARAMETER register per GPIO port.
ATUC64/128/256L3/4U 19.7.22 Name: Version Register VERSION Access Type: Read-only Offset: 0x1FC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 19.8 Module Configuration The specific configuration for each GPIO instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 19-3. GPIO Configuration Feature GPIO Number of GPIO ports 2 Number of peripheral functions 8 Table 19-4. Implemented Pin Functions Pin Function Implemented Notes Pull-up On all pins Controlled by PUER or peripheral Table 19-5.
ATUC64/128/256L3/4U 20. Universal Synchronous Asynchronous Receiver Transmitter (USART) Rev: 4.4.0.6 20.1 Features • Configurable baud rate generator • 5- to 9-bit full-duplex, synchronous and asynchronous, serial communication • • • • 20.2 – 1, 1.
ATUC64/128/256L3/4U buffer management without processor intervention. Automatic echo, remote-, and local loopback -test modes are also supported. 20.3 Block Diagram Figure 20-1. USART Block Diagram Peripheral DMA Controller Channel Channel I/O Controller USART RXD Receiver RTS Interrupt Controller USART Interrupt TXD Transmitter CTS CLK_USART Power Manager DIV BaudRate Generator CLK CLK_USART/DIV User Interface Peripheral bus Table 20-1.
ATUC64/128/256L3/4U 20.4 I/O Lines Description Table 20-2.
ATUC64/128/256L3/4U 20.6 Functional Description 20.6.1 Baud Rate Generator The baud rate generator provides the bit period clock named the Baud Rate Clock to both receiver and transmitter. It is based on a 16-bit divider, which is specified in the Clock Divider field in the Baud Rate Generator Register (BRGR.CD). A non-zero value enables the generator, and if CD is one, the divider is bypassed and inactive. The Clock Selection field in the Mode Register (MR.
ATUC64/128/256L3/4U Table 20-3. Baud Rate Example (OVER=0) Source Clock (Hz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.
ATUC64/128/256L3/4U Figure 20-3. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP CLK_USART CLK_USART/DIV CLK Reserved CD CLK 0 1 16-bit Counter 2 glitch-free logic 3 FIDI >1 1 0 OVER SYNC 0 Sampling Divider 0 0 BaudRate Clock 1 1 SYNC USCLKS = 3 20.6.1.4 Sampling Clock Baud Rate in Synchronous and SPI Mode If the USART is configured to operate in synchronous mode, the selected clock is divided by the BRGR.CD field. This does not apply when CLK is selected.
ATUC64/128/256L3/4U 20.6.3 Synchronous and Asynchronous Modes 20.6.3.1 Transmitter Operations The transmitter performs equally in both synchronous and asynchronous operating modes (MR.SYNC). One start bit, up to 9 data bits, an optional parity bit, and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the serial clock. The number of data bits is selected by the Character Length field (MR.CHRL) and the MR.MODE9 bit.
ATUC64/128/256L3/4U The number of data bits, endianess, parity mode, and stop bits are selected by the same bits and fields as for the transmitter (MR.CHRL, MODE9, MSBF, PAR, and NBSTOP). The synchronization mechanism will only consider one stop bit, regardless of the used protocol, and when the first stop bit has been sampled, the receiver will automatically begin looking for a new start bit, enabling resynchronization even if there is a protocol miss-match.
ATUC64/128/256L3/4U Figure 20-8. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 Stop Bit D7 Parity Bit 20.6.3.4 Receiver Operations When a character reception is completed, it is transferred to the Received Character field in the Receive Holding Register (RHR.RXCHR), and the Receiver Ready bit in the Channel Status Register (CSR.RXRDY) is set.
ATUC64/128/256L3/4U The receiver will report parity errors in CSR.PARE, unless parity is disabled. Writing a one to CR.RSTSTA will clear PARE. See Figure 20-10 Figure 20-10. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write CR PARE RXRDY 20.6.3.6 Multidrop Mode If PAR is either 0x6 or 0x7, the USART runs in Multidrop mode. This mode differentiates data and address characters. Data has the parity bit zero and addresses have a one.
ATUC64/128/256L3/4U Table 20-5. 20.6.3.8 Maximum Baud Rate Dependent Timeguard Durations Baud Rate (bit/sec) Bit time (µs) Timeguard (ms) 1 200 833 212.50 9 600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 Receiver Time-out The Time-out Value field in the Receiver Time-out Register (RTOR.TO) enables handling of variable-length frames by detection of selectable idle durations on the RXD line.
ATUC64/128/256L3/4U 20.6.3.9 Baud Rate (bit/sec) Bit Time (µs) Time-out (ms) 9 600 104 6 827 14400 69 4 551 19200 52 3 413 28800 35 2 276 33400 30 1 962 56000 18 1 170 57600 17 1 138 200000 5 328 Framing Error The receiver is capable of detecting framing errors. A framing error has occurred if a stop bit reads as zero. This can occur if the transmitter and receiver are not synchronized. A framing error is reported by CSR.
ATUC64/128/256L3/4U Figure 20-14. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Break Transmission STTBRK = 1 End of Break STPBRK = 1 Write CR TXRDY TXEMPTY 20.6.3.11 Receive Break A break condition is assumed when incoming data, parity, and stop bits are zero. This corresponds to a framing error, but FRAME will remain zero while the Break Received/End Of Break bit (CSR.RXBRK) is set. Writing a one to CR.RSTSTA will clear RXBRK.
ATUC64/128/256L3/4U Figure 20-16. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write CR RTS RXBUFF Figure 20-17. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD Figure 20-18. 20.6.4 SPI Mode The USART features a Serial Peripheral Interface (SPI) link compliant mode, supporting synchronous, full-duplex communication, in both master and slave mode. Writing 0xE (master) or 0xF (slave) to MR.MODE will enable this mode.
ATUC64/128/256L3/4U • The Clock Selection field (MR.USCLKS) must not equal 0x3 (external clock, CLK). • The Clock Output Select bit (MR.CLKO) must be one. • The BRGR.CD field must be at least 0x4. • If USCLKS is one (internal divided clock, CLK_USART/DIV), the value in CD has to be even, ensuring a 50:50 duty cycle. CD can be odd if USCLKS is zero (internal clock, CLK_USART). In SPI Slave Mode: • CLK frequency must be at least four times lower than the system clock. 20.6.4.
ATUC64/128/256L3/4U Figure 20-20. SPI Transfer Format (CPHA=0, 8 bits per transfer) CLK cycle (for reference) 1 2 3 4 5 6 7 8 CLK (CPOL= 0) CLK (CPOL= 1) MOSI SPI Master -> TXD SPI Slave -> RXD MSB 6 5 4 3 2 1 LSB MISO SPI Master -> RXD SPI Slave -> TXD MSB 6 5 4 3 2 1 LSB NSS SPI Master -> RTS SPI Slave -> CTS 20.6.4.4 Receiver and Transmitter Control See ”Transmitter Operations” on page 440, and ”Receiver Operations” on page 442. 20.6.4.
ATUC64/128/256L3/4U customizable response data lengths, and requires minimal CPU resources. Writing 0xA (master) or 0xB (slave) to MR.MODE enables this mode. 20.6.5.1 Modes of operation Changing LIN mode after initial configuration has to be followed by a transceiver software reset in order to avoid unpredictable behavior. 20.6.5.2 Receiver and Transmitter Control See Section “20.6.2” on page 439. 20.6.5.
ATUC64/128/256L3/4U Figure 20-22. Header Reception Baud Rate Clock RXD Break Field 13 dominant bits (at 0) LINID Break Delimiter 1 recessive bit (at 1) Start 1 Bit 0 1 0 1 0 1 0 Stop Stop Start ID0 ID1 ID2 ID3 ID4 ID5 ID6 ID7 Bit Bit Bit Synch Byte = 0x55 US_LINIR Write US_CR With RSTSTA=1 20.6.5.7 Slave Node Synchronization Synchronization is only done by the slave. If the Sync field is not 0x55, an Inconsistent Sync Field error (CSR.LINISFE) is generated.
ATUC64/128/256L3/4U • The oversampling mode (OVER=0 => 16x, or OVER=1 => 8x) The following formula is used to calculate synchronization deviation, where FSLAVE is the real slave node clock frequency, and FTOL_UNSYNC is the difference between FNom and FSLAVE According to the LIN specification, FTOL_UNSYNCH may not exceed ±15%, and the bit rates between two nodes must be within ±2% of each other, resulting in a maximal BaudRate_deviation of ±1%.
ATUC64/128/256L3/4U • PARDIS=0: During header transmission, the parity bits are computed and in the shift register they replace bits six and seven from IDCHR. During header reception, the parity bits are checked and can generate a LIN Identifier Parity Error (see Section 20.6.6). Bits six and seven in IDCHR read as zero when receiving. • PARDIS=1: During header transmission, all the bits in IDCHR are sent on the bus. During header reception, all the bits in IDCHR are updated with the received Identifier.
ATUC64/128/256L3/4U • DLM=1: the response data length is defined by the Identifier bits according to the table below. Table 20-8. 20.6.5.11 Response Data Length if DLM = 1 IDCHR[5] IDCHR[4] Response Data Length [bytes] 0 0 2 0 1 2 1 0 4 1 1 8 Checksum The last frame field is the checksum. It is configured by the Checksum Type (LINMR.CHKTYP), and the Checksum Disable (LINMR.CHKDIS) bits. TXRDY will not be set after the last THR data write if enabled.
ATUC64/128/256L3/4U • TFrame_Maximum = 1.4 x (THeader_Nominal + TResponse_Nominal + 1)(Note:) Note: The term “+1” leads to an integer result for TFrame_Max (LIN Specification 1.3) If the Checksum is sent (CHKDIS=0): • TResponse_Nominal = 10 x (NData + 1) • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1 + 1) + 1) • TFrame_Maximum = 77 + 14 x DLC If the Checksum is not sent (CHKDIS=1): • TResponse_Nominal = 10 x NData • TFrame_Maximum = 1.4 x (34 + 10 x (DLC + 1) + 1) • TFrame_Maximum = 63 + 14 x DLC 20.6.
ATUC64/128/256L3/4U • Case 1: NACT=PUBLISH, the USART sends a response – Wait until TXRDY is a one – Send a byte by writing to THR.TXCHR – Repeat the two previous steps until there is no more data to send – Wait until CSR.LINTC is a one – Check for LIN errors • Case 2: NACT=SUBSCRIBE, the USART receives a response – Wait until RXRDY is a one – Read RHR.
ATUC64/128/256L3/4U Figure 20-28. Master Node Configuration, NACT=SUBSCRIBE Frame slot = TFrame_Maximum Frame Header Break Synch Data3 Interframe space Response space Protected Identifier Response Data 1 Data N-1 Data N Checksum TXRDY FSDIS=1 FSDIS=0 RXRDY Write LINIR Read RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 20-29.
ATUC64/128/256L3/4U Figure 20-30. Slave Node Configuration, NACT=PUBLISH Break Synch Protected Identifier Data 1 Data N-1 Data N Checksum Data N Checksum TXRDY RXRDY LINIDRX Read LINID Write THR Data 1 Data 2 Data 3 Data N LINTC Figure 20-31. Slave Node Configuration, NACT=SUBSCRIBE Break Synch Protected Identifier Data 1 Data N-1 TXRDY RXRDY LINIDRX Read LINID Read RHR Data 1 Data N-2 Data N-1 Data N LINTC Figure 20-32.
ATUC64/128/256L3/4U 20.6.8.1 Master Node Configuration The Peripheral DMA Controller Mode bit (LINMR.PDCM) allows the user to select configuration: • PDCM=0: LIN configuration must be written to LINMR, it is not stored in the write buffer. • PDCM=1: LIN configuration is written by the DMA Controller to THR, and is stored in the write buffer. Since data transfer size is a byte, the transfer is split into two accesses.
ATUC64/128/256L3/4U 20.6.8.2 Slave Node Configuration In this mode, the Peripheral DMA Controller transfers only data. The user reads the Identifier from LINIR, and selects LIN mode by writing to LINMR. When NACT=PUBLISH the data is in the write buffer, while the read buffer contains the data when NACT=SUBSCRIBE.
ATUC64/128/256L3/4U 20.6.11 Test Modes The internal loopback feature enables on-board diagnostics, and allows the USART to operate in three different test modes, with reconfigured pin functionality, as shown below. 20.6.11.1 Normal Mode During normal operation, a receivers RXD pin is connected to a transmitters TXD pin. Figure 20-36. Normal Mode Configuration RXD Receiver TXD Transmitter 20.6.11.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission.
ATUC64/128/256L3/4U Figure 20-39. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 20.6.12 Write Protection Registers To prevent single software errors from corrupting USART behavior, certain address spaces can be write-protected by writing the correct Write Protect KEY and a one to the Write Protect Enable bit in the Write Protect Mode Register (WPMR.WPKEY, and WPMR.WPEN). Disabling the write protection is done by writing the correct key, and a zero to WPEN.
ATUC64/128/256L3/4U 20.7 User Interface Table 20-10.
ATUC64/128/256L3/4U 20.7.1 Name: Control Register CR Access Type: Write-only Offset: 0x0 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 LINWKUP 20 LINABT 19 RTSDIS/RCS 18 RTSEN/FCS 17 – 16 – 15 RETTO 14 RSTNACK 13 – 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • LINWKUP: Send LIN Wakeup Signal Writing a zero to this bit has no effect.
ATUC64/128/256L3/4U • STPBRK: Stop Break Writing a zero to this bit has no effect. Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least 12 bit periods. No effect if no break is being transmitted. • STTBRK: Start Break Writing a zero to this bit has no effect. Writing a one to this bit will start transmission of break characters when current characters present in THR and the transmit shift register have been sent.
ATUC64/128/256L3/4U 20.7.2 Name: Mode Register MR Access Type: Read-write Offset: 0x4 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 25 – 24 23 – 22 – 21 – 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF/CPOL 14 13 12 11 10 PAR 9 8 SYNC/CPHA 4 3 2 1 0 15 CHMODE 7 NBSTOP 6 CHRL 5 USCLKS MODE This register can only be written if the WPEN bit is cleared in the Write Protect Mode Register. • INACK: Inhibit Non Acknowledge 0: The NACK is generated.
ATUC64/128/256L3/4U • CHMODE: Channel Mode Table 20-11. CHMODE Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver input. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin. • NBSTOP: Number of Stop Bits Table 20-12. NBSTOP Asynchronous (SYNC=0) Synchronous (SYNC=1) 0 0 1 stop bit 1 stop bit 0 1 1.
ATUC64/128/256L3/4U • CHRL: Character Length. Table 20-14. CHRL Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits • USCLKS: Clock Selection Table 20-15. USCLKS Note: Selected Clock 0 0 CLK_USART 0 1 CLK_USART/DIV(1) 1 0 Reserved 1 1 CLK 1. The value of DIV is device dependent. Please refer to the Module Configuration section at the end of this chapter. • MODE Table 20-16.
ATUC64/128/256L3/4U 20.7.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x8 Reset Value: 0x00000000 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 20.7.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0xC Reset Value: 0x00000000 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 20.7.5 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 – 30 – 29 LINSNRE 28 LINCE 27 LINIPE 26 LINISFE 25 LINBE 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 – 17 – 16 – 15 LINTC 14 LINID 13 NACK/LINBK 12 RXBUFF 11 – 10 ITER/UNRE 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 – 3 – 2 RXBRK 1 TXRDY 0 RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 20.7.
ATUC64/128/256L3/4U 1: The Buffer Full signal from the Peripheral DMA Controller channel is active. • ITER/UNRE: Max number of Repetitions Reached or SPI Underrun Error If USART does not operate in SPI Slave Mode: ITER=0: Maximum number of repetitions has not been reached since the last RSTSTA. ITER=1: Maximum number of repetitions has been reached since the last RSTSTA. If USART operates in SPI Slave Mode: UNRE=0: No SPI underrun error has occurred since the last RSTSTA.
ATUC64/128/256L3/4U 20.7.7 Name: Receiver Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR[8] 7 6 5 4 3 2 1 0 RXCHR[7:0] • RXCHR: Received Character Last received character.
ATUC64/128/256L3/4U 20.7.8 Name: Transmitter Holding Register THR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR[8] 7 6 5 4 3 2 1 0 TXCHR[7:0] • TXCHR: Character to be Transmitted If TXRDY is zero this field contains the next character to be transmitted.
ATUC64/128/256L3/4U 20.7.9 Name: Baud Rate Generator Register BRGR Access Type: Read-write Offset: 0x20 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP 16 15 14 13 12 11 10 9 8 3 2 1 0 CD[15:8] 7 6 5 4 CD[7:0] This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • FP: Fractional Part 0: Fractional divider is disabled.
ATUC64/128/256L3/4U 20.7.10 Name: Receiver Time-out Register RTOR Access Type: Read-write Offset: 0x24 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 TO[16] 15 14 13 12 11 10 9 8 3 2 1 0 TO[15:8] 7 6 5 4 TO[7:0] This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • TO: Time-out Value 0: The receiver Time-out is disabled.
ATUC64/128/256L3/4U 20.7.11 Name: Transmitter Timeguard Register TTGR Access Type: Read-write Offset: 0x28 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG This register can only be written to if write protection is disabled, see ”Write Protect Mode Register” on page 482. • TG: Timeguard Value 0: The transmitter Timeguard is disabled.
ATUC64/128/256L3/4U 20.7.12 Name: LIN Mode Register LINMR Access Type: Read-write Offset: 0x54 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 PDCM 15 14 13 12 11 10 9 8 3 CHKDIS 2 PARDIS 1 DLC 7 WKUPTYP 6 FSDIS 5 DLM 4 CHKTYP 0 NACT • PDCM: Peripheral DMA Controller Mode 0: The LIN mode register is not written by the Peripheral DMA Controller.
ATUC64/128/256L3/4U Table 20-18. 0 1 SUBSCRIBE: The USART receives the response. 1 0 IGNORE: The USART does not transmit and does not receive the response.
ATUC64/128/256L3/4U 20.7.13 Name: LIN Identifier Register LINIR Access Type: Read-write or Read-only Offset: 0x58 Reset Value: 0x00000000 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IDCHR • IDCHR: Identifier Character If USART is in LIN master mode, the IDCHR field is read-write, and its value is the Identifier character to be transmitted.
ATUC64/128/256L3/4U 20.7.14 Write Protect Mode Register Register Name: WPMR Access Type: Read-write Offset: 0xE4 Reset Value: See Table 20-10 31 30 29 28 27 WPKEY[23:16] 26 25 24 23 22 21 20 19 18 17 16 11 10 9 8 3 — 2 — 1 — 0 WPEN WPKEY[15:8] 15 14 13 12 WPKEY[7:0] 7 — 6 — 5 — 4 — • WPKEY: Write Protect KEY Has to be written to 0x555341 (“USA” in ASCII) in order to successfully write WPEN. Always reads as zero. • WPEN: Write Protect Enable 0 = Write protection disabled.
ATUC64/128/256L3/4U 20.7.15 Write Protect Status Register Register Name: WPSR Access Type: Read-only Offset: 0xE8 Reset Value: See Table 20-10 31 — 30 — 29 — 28 — 27 — 26 — 25 — 24 — 23 22 21 20 19 WPVSRC[15:8] 18 17 16 15 14 13 12 11 10 9 8 3 — 2 — 1 — 0 WPVS WPVSRC[7:0] 7 — 6 — 5 — 4 — • WPVSRC: Write Protect Violation Source If WPVS=1 this field indicates which write-protected register was unsuccessfully written to, either by address offset or code.
ATUC64/128/256L3/4U 20.7.16 Version Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 18 17 16 15 – 14 – 13 – 12 – 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 MFN 1 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version of the module. No functionality associated.
ATUC64/128/256L3/4U 20.8 Module Configuration The specific configuration for each USART instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 20-19. USART Configuration Feature USART0 USART1 USART2 USART3 17 bit 17 bit 17 bit 17 bit 8 8 8 8 Receiver Time-out Counter Size (Size of the RTOR.TO field) DIV Value for divided CLK_USART Table 20-20.
ATUC64/128/256L3/4U 21. Serial Peripheral Interface (SPI) Rev: 2.1.1.3 21.
ATUC64/128/256L3/4U 21.3 Block Diagram Figure 21-1. SPI Block Diagram Peripheral DMA Controller Peripheral Bus SPCK MISO CLK_SPI MOSI Spi Interface I/O Controller NPCS0/NSS NPCS1 NPCS2 Interrupt Control NPCS3 SPI Interrupt 21.4 Application Block Diagram Figure 21-2.
ATUC64/128/256L3/4U 21.5 I/O Lines Description Table 21-1. I/O Lines Description Type 21.6 Pin Name Pin Description Master Slave MISO Master In Slave Out Input Output MOSI Master Out Slave In Output Input SPCK Serial Clock Output Input NPCS1-NPCS3 Peripheral Chip Selects Output Unused NPCS0/NSS Peripheral Chip Select/Slave Select Output Input Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 21.6.
ATUC64/128/256L3/4U 21.7.2 Data Transfer Four combinations of polarity and phase are available for data transfers. The clock polarity is configured with the Clock Polarity bit in the Chip Select Registers (CSRn.CPOL). The clock phase is configured with the Clock Phase bit in the CSRn registers (CSRn.NCPHA). These two bits determine the edges of the clock signal on which data is driven and sampled.
ATUC64/128/256L3/4U Figure 21-4. SPI Transfer Format (NCPHA = 0, 8 bits per transfer) SPCK cycle (for reference) 1 2 3 4 5 6 7 8 SPCK (CPOL = 0) SPCK (CPOL = 1) MOSI (from master) MISO (from slave) *** MSB 6 5 4 3 2 1 MSB 6 5 4 3 2 1 LSB LSB NSS (to slave) *** Not Defined, but normaly LSB of previous character transmitted 21.7.3 Master Mode Operations When configured in master mode, the SPI uses the internal programmable baud rate generator as clock source.
ATUC64/128/256L3/4U Figure 21-5 on page 491shows a block diagram of the SPI when operating in master mode. Figure 21-6 on page 492 shows a flow chart describing how transfers are handled. 21.7.3.1 Master mode block diagram Figure 21-5. Master Mode Block Diagram CSR0..3 SCBR CLK_SPI Baud Rate Generator SPCK SPI Clock RXFIFOEN RDRF OVRES RDR RD CSR0..3 BITS NCPHA CPOL LSB MISO 0 1 4 – Character FIFO MSB Shift Register MOSI TDR TD TDRE RXFIFOEN RDR CSR0..
ATUC64/128/256L3/4U 21.7.3.2 Master mode flow diagram Figure 21-6. Master Mode Flow Diagram SPI Enable - NPCS defines the current Chip Select - CSAAT, DLYBS, DLYBCT refer to the fields of the Chip Select Register corresponding to the Current Chip Select - When NPCS is 0xF, CSAAT is 0.
ATUC64/128/256L3/4U 21.7.3.3 Clock generation The SPI Baud rate clock is generated by dividing the CLK_SPI , by a value between 1 and 255. This allows a maximum operating baud rate at up to CLK_SPI and a minimum operating baud rate of CLK_SPI divided by 255. Writing the Serial Clock Baud Rate field in the CSRn registers (CSRn.SCBR) to zero is forbidden. Triggering a transfer while CSRn.SCBR is zero can lead to unpredictable results. At reset, CSRn.
ATUC64/128/256L3/4U 21.7.3.5 Peripheral selection The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS signals are high before and after each transfer.
ATUC64/128/256L3/4U to an interrupt, and thus might lead to difficulties for interfacing with some serial peripherals requiring the chip select line to remain active during a full set of transfers. To facilitate interfacing with such devices, the CSRn registers can be configured with the Chip Select Active After Transfer bit written to one (CSRn.CSAAT) . This allows the chip select lines to remain in their current state (low = active) until transfer to another peripheral is required. When the CSRn.
ATUC64/128/256L3/4U Figure 21-8. Peripheral Deselection CSAAT = 0 and CSNAAT = 0 TDRE NPCS[0..3] CSAAT = 1 and CSNAAT= 0 / 1 DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS = A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A A A A DLYBCS A DLYBCS PCS=A PCS = A Write TDR TDRE NPCS[0..3] DLYBCT DLYBCT A B B A DLYBCS DLYBCS PCS = B PCS = B Write TDR CSAAT = 0 and CSNAAT = 0 CSAAT = 0 and CSNAAT = 1 DLYBCT DLYBCT TDRE NPCS[0..
ATUC64/128/256L3/4U register (MR.MODFDIS). In systems with open-drain I/O lines, a mode fault is detected when a low level is driven by an external master on the NPCS0/NSS signal. When a mode fault is detected, the Mode Fault Error bit in the SR (SR.MODF) is set until the SR is read and the SPI is automatically disabled until re-enabled by writing a one to the SPI Enable bit in the CR register (CR.SPIEN). By default, the mode fault detection circuitry is enabled.
ATUC64/128/256L3/4U Figure 21-9.
ATUC64/128/256L3/4U 21.8 User Interface Table 21-3.
ATUC64/128/256L3/4U 21.8.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - FLUSHFIFO 7 6 5 4 3 2 1 0 SWRST - - - - - SPIDIS SPIEN • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
ATUC64/128/256L3/4U 21.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 DLYBCS 23 22 21 20 - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LLB RXFIFOEN - MODFDIS - PCSDEC PS MSTR PCS • DLYBCS: Delay Between Chip Selects This field defines the delay from NPCS inactive to the activation of another NPCS.
ATUC64/128/256L3/4U 0: The FIFO is not used in reception (only one character can be stored in the SPI). • MODFDIS: Mode Fault Detection 1: Mode fault detection is disabled. If the I/O controller does not have open-drain capability, mode fault detection must be disabled for proper operation of the SPI. 0: Mode fault detection is enabled. • PCSDEC: Chip Select Decode 0: The chip selects are directly connected to a peripheral device. 1: The four chip select lines are connected to a 4- to 16-bit decoder.
ATUC64/128/256L3/4U 21.8.3 Name: Receive Data Register RDR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RD[15:8] 7 6 5 4 RD[7:0] • RD: Receive Data Data received by the SPI Interface is stored in this register right-justified. Unused bits read zero.
ATUC64/128/256L3/4U 21.8.4 Name: Transmit Data Register TDR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - LASTXFER 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 PCS 11 10 9 8 3 2 1 0 TD[15:8] 7 6 5 4 TD[7:0] • LASTXFER: Last Transfer 1: The current NPCS will be deasserted after the character written in TD has been transferred. When CSRn.
ATUC64/128/256L3/4U 21.8.5 Name: Status Register SR Access Type: Read-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - SPIENS 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF • SPIENS: SPI Enable Status 1: This bit is set when the SPI is enabled. 0: This bit is cleared when the SPI is disabled.
ATUC64/128/256L3/4U 21.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 21.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 21.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - UNDES TXEMPTY NSSR 7 6 5 4 3 2 1 0 - - - - OVRES MODF TDRE RDRF 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 21.8.9 Name: Chip Select Register 0 CSR0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
ATUC64/128/256L3/4U 21.8.10 Name: Chip Select Register 1 CSR1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
ATUC64/128/256L3/4U 21.8.11 Name: Chip Select Register 2 CSR2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
ATUC64/128/256L3/4U 21.8.12 Name: Chip Select Register 3 CSR3 Access Type: Read/Write Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CSAAT CSNAAT NCPHA CPOL DLYBCT 23 22 21 20 DLYBS 15 14 13 12 SCBR 7 6 5 BITS 4 • DLYBCT: Delay Between Consecutive Transfers This field defines the delay between two consecutive transfers with the same peripheral without removing the chip select.
ATUC64/128/256L3/4U • BITS: Bits Per Transfer The BITS field determines the number of data bits transferred. Reserved values should not be used. BITS Bits Per Transfer 0000 8 0001 9 0010 10 0011 11 0100 12 0101 13 0110 14 0111 15 1000 16 1001 4 1010 5 1011 6 1100 7 1101 Reserved 1110 Reserved 1111 Reserved • CSAAT: Chip Select Active After Transfer 1: The Peripheral Chip Select does not rise after the last transfer is achieved.
ATUC64/128/256L3/4U CPOL is used to determine the inactive state value of the serial clock (SPCK). It is used with NCPHA to produce the required clock/data relationship between master and slave devices.
ATUC64/128/256L3/4U 21.8.
ATUC64/128/256L3/4U 21.8.
ATUC64/128/256L3/4U 21.8.15 Features Register Register Name: FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - SWIMPL FIFORIMPL BRPBHSB CSNAATIMPL EXTDEC 15 14 13 12 11 10 9 8 LENNCONF 7 6 5 4 PHZNCONF PHCONF PPNCONF PCONF LENCONF 3 2 1 0 NCS • SWIMPL: Spurious Write Protection Implemented • • • • • • • • 0: Spurious write protection is not implemented.
ATUC64/128/256L3/4U • PPNCONF: Polarity Positive if Polarity not Configurable 0: If polarity is not configurable, polarity is negative. 1: If polarity is not configurable, polarity is positive. • PCONF: Polarity Configurable 0: Polarity is not configurable. 1: Polarity is configurable. • NCS: Number of Chip Selects This field indicates the number of chip selects implemented.
ATUC64/128/256L3/4U 21.8.16 Version Register Register Name: VERSION Access Type: Read-only Offset: 0xFC Reset Value: – 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 MFN 11 10 VERSION[11:8] 7 6 5 4 3 2 1 0 VERSION[7:0] • MFN Reserved. No functionality associated. • VERSION Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 21.9 Module Configuration The specific configuration for each SPI instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 21-4. SPI Clock Name Module Name Clock Name Description SPI CLK_SPI Clock for the SPI bus interface Table 21-5.
ATUC64/128/256L3/4U 22. Two-wire Master Interface (TWIM) Rev.: 1.1.0.1 22.1 Features • Compatible with I²C standard • • • • • • 22.
ATUC64/128/256L3/4U Table 22-2 lists the compatibility level of the Atmel Two-wire Master Interface and a full SMBus compatible master. Table 22-2. 22.3 SMBus Standard Atmel TWIM Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Host Functionality Supported Packet Error Checking Supported List of Abbreviations Table 22-3. 22.
ATUC64/128/256L3/4U 22.5 Application Block Diagram Figure 22-2. Application Block Diagram VDD Rp Rp Rp TWD TWI Master TWCK TWALM Atmel TWI serial EEPROM I2C RTC I2C LCD controller I2C temp sensor Slave 1 Slave 2 Slave 3 Slave 4 Rp: pull-up value as given by the I2C Standard 22.6 I/O Lines Description Table 22-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 22.
ATUC64/128/256L3/4U 22.7.3 Clocks The clock for the TWIM bus interface (CLK_TWIM) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the TWIM before disabling the clock, to avoid freezing the TWIM in an undefined state. 22.7.4 DMA The TWIM DMA handshake interface is connected to the Peripheral DMA Controller.
ATUC64/128/256L3/4U 22.8 22.8.1 Functional Description Transfer Format The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure 22-4). Each transfer begins with a START condition and terminates with a STOP condition (see Figure 22-4). • A high-to-low transition on the TWD line while TWCK is high defines the START condition.
ATUC64/128/256L3/4U 22.8.2.1 Clock Generation The Clock Waveform Generator Register (CWGR) is used to control the waveform of the TWCK clock. CWGR must be written so that the desired TWI bus timings are generated. CWGR describes bus timings as a function of cycles of a prescaled clock. The clock prescaling can be selected through the Clock Prescaler field in CWGR (CWGR.EXP).
ATUC64/128/256L3/4U 22.8.2.2 Setting up and Performing a Transfer Operation of the TWIM is mainly controlled by the Control Register (CR) and the Command Register (CMDR). TWIM status is provided in the Status Register (SR). The following list presents the main steps in a typical communication: 1. Before any transfers can be performed, bus timings must be configured by writing to the Clock Waveform Generator Register (CWGR).
ATUC64/128/256L3/4U TWI transfers require the slave to acknowledge each received data byte. During the acknowledge clock pulse (9th pulse), the master releases the data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse and sets the Data Acknowledge bit (DNACK) in the Status Register if the slave does not acknowledge the data byte.
ATUC64/128/256L3/4U 1. Wait until RHR is empty, stretching low period of TWCK. SR.RXRDY indicates the state of RHR. Software or the Peripheral DMA Controller must read any data byte present in RHR. 2. Release TWCK generating a clock that the slave uses to transmit a data byte. 3. Place the received data byte in RHR, set RXRDY. 4. If NBYTES=0, generate a NAK after the data byte, otherwise generate an ACK. 5. Decrement NBYTES 6. If (NBYTES==0) and STOP=1, transmit STOP condition.
ATUC64/128/256L3/4U 22.8.5 Using the Peripheral DMA Controller The use of the Peripheral DMA Controller significantly reduces the CPU load. The user can set up ring buffers for the Peripheral DMA Controller, containing data to transmit or free buffer space to place received data. To assure correct behavior, respect the following programming sequences: 22.8.5.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2.
ATUC64/128/256L3/4U Figure 22-10. User Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 22-11.
ATUC64/128/256L3/4U As for single data transfers, the TXRDY and RXRDY bits in the Status Register indicates when data to transmit can be written to THR, or when received data can be read from RHR. Transfer of data to THR and from RHR can also be done automatically by DMA, see Section 22.8.5 22.8.7.1 Write Followed by Write Consider the following transfer: START, DADR+W, DATA+A, DATA+A, REPSTART, DADR+W, DATA+A, DATA+A, STOP. To generate this transfer: 1.
ATUC64/128/256L3/4U Figure 22-12. Combining a Write and Read Transfer THR DATA0 DATA1 RHR TWD DATA2 S DADR W A DATA0 A DATA1 NA Sr R DADR A DATA2 A DATA3 DATA3 A P SR.IDLE 1 TXRDY RXRDY To generate this transfer: 1. Write CMDR with START=1, STOP=0, DADR, NBYTES=2 and READ=0. 2. Write NCMDR with START=1, STOP=1, DADR, NBYTES=2 and READ=1. 3. Wait until SR.TXRDY==1, then write first data byte to transfer to THR. 4. Wait until SR.
ATUC64/128/256L3/4U 22.8.8 Ten Bit Addressing Writing a one to CMDR.TENBIT enables 10-bit addressing in hardware. Performing transfers with 10-bit addressing is similar to transfers with 7-bit addresses, except that bits 9:7 of CMDR.SADR must be written appropriately. In Figure 22-14 and Figure 22-15, the grey boxes represent signals driven by the master, the white boxes are driven by the slave. 22.8.8.1 Master Transmitter To perform a master transmitter transfer: 1.
ATUC64/128/256L3/4U 22.8.9.1 Packet Error Checking Each SMBus transfer can optionally end with a CRC byte, called the PEC byte. Writing a one to CMDR.PECEN enables automatic PEC handling in the current transfer. Transfers with and without PEC can freely be intermixed in the same system, since some slaves may not support PEC. The PEC LFSR is always updated on every bit transmitted or received, so that PEC handling on combined transfers will be correct.
ATUC64/128/256L3/4U 22.8.10 Identifying Bus Events This chapter lists the different bus events, and how they affect bits in the TWIM registers. This is intended to help writing drivers for the TWIM. Table 22-5. Bus Events Event Effect Master transmitter has sent a data byte SR.THR is cleared. Master receiver has received a data byte SR.RHR is set. Start+Sadr sent, no ack received from slave SR.ANAK is set. SR.CCOMP not set. CMDR.VALID remains set. STOP automatically transmitted on bus.
ATUC64/128/256L3/4U 22.9 User Interface Table 22-6.
ATUC64/128/256L3/4U 22.9.1 Name: Control Register CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - STOP 7 6 5 4 3 2 1 0 SWRST - SMDIS SMEN - - MDIS MEN • STOP: Stop the Current Transfer Writing a one to this bit terminates the current transfer, sending a STOP condition after the shifter has become idle.
ATUC64/128/256L3/4U 22.9.2 Name: Clock Waveform Generator Register CWGR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 - 23 29 28 27 26 EXP 22 21 25 24 DATA 20 19 18 17 16 11 10 9 8 3 2 1 0 STASTO 15 14 13 12 HIGH 7 6 5 4 LOW • EXP: Clock Prescaler Used to specify how to prescale the TWCK clock.
ATUC64/128/256L3/4U 22.9.3 Name: SMBus Timing Register SMBTR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 THMAX 15 14 13 12 TLOWM 7 6 5 4 TLOWS • EXP: SMBus Timeout Clock Prescaler Used to specify how to prescale the TIM and TLOWM counters in SMBTR.
ATUC64/128/256L3/4U 22.9.4 Name: Command Register CMDR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 - 23 29 28 - 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ • ACKLAST: ACK Last Master RX Byte 0: Causes the last byte in master receive mode (when NBYTES has reached 0) to be NACKed.
ATUC64/128/256L3/4U Write this bit to one if the command in CMDR performs a repeated start to the same slave address as addressed in the previous transfer in order to enter master receiver mode. Write this bit to zero otherwise. • TENBIT: Ten Bit Addressing Mode 0: Use 7-bit addressing mode. 1: Use 10-bit addressing mode. Must not be used when the TWIM is in SMBus mode. • SADR: Slave Address Address of the slave involved in the transfer. Bits 9-7 are don’t care if 7-bit addressing is used.
ATUC64/128/256L3/4U 22.9.5 Name: Next Command Register NCMDR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 - 29 28 - 23 22 21 20 27 26 25 24 - - ACKLAST PECEN 19 18 17 16 10 9 8 NBYTES 15 14 13 12 11 VALID STOP START REPSAME TENBIT 7 6 5 4 3 SADR[6:0] SADR[9:7] 2 1 0 READ This register is identical to CMDR. When the VALID bit in CMDR becomes 0, the content of NCMDR is copied into CMDR, clearing the VALID bit in NCMDR.
ATUC64/128/256L3/4U 22.9.6 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
ATUC64/128/256L3/4U 22.9.7 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data to Transmit Write data to be transferred on the TWI bus here.
ATUC64/128/256L3/4U 22.9.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - MENB 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY • MENB: Master Interface Enable 0: Master interface is disabled. 1: Master interface is enabled.
ATUC64/128/256L3/4U • IDLE: Master Interface is Idle This bit is one when no command is in progress, and no command waiting to be issued. Otherwise, this bit is cleared. • CCOMP: Command Complete This bit is one when the current command has completed successfully. This bit is zero if the command failed due to conditions such as a NAK receved from slave. This bit is cleared by writing 1 to the corresponding bit in the Status Clear Register (SCR).
ATUC64/128/256L3/4U 22.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 22.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 22.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - BUSFREE IDLE CCOMP CRDY TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 22.9.12 Name: Status Clear Register SCR Access Type : Write-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - STOP PECERR TOUT SMBALERT ARBLST DNAK ANAK 7 6 5 4 3 2 1 0 - - - - CCOMP - - - Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 22.9.
ATUC64/128/256L3/4U 22.9.14 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 22.10 Module Configuration The specific configuration for each TWIM instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 22-7. Module Clock Name Module Name Clock Name Description TWIM0 CLK_TWIM0 Clock for the TWIM0 bus interface TWIM1 CLK_TWIM1 Clock for the TWIM1 bus interface Table 22-8.
ATUC64/128/256L3/4U 23. Two-wire Slave Interface (TWIS) Rev.: 1.2.0.1 23.1 Features • Compatible with I²C standard • • • • • • 23.
ATUC64/128/256L3/4U Below, Table 23-2 lists the compatibility level of the Atmel Two-wire Slave Interface and a full SMBus compatible device. Table 23-2. 23.3 SMBus Standard Atmel TWIS Bus Timeouts Supported Address Resolution Protocol Supported Alert Supported Packet Error Checking Supported List of Abbreviations Table 23-3. 23.
ATUC64/128/256L3/4U 23.5 Application Block Diagram Figure 23-2. Application Block Diagram VDD Rp Host with TWI Interface Rp TWD TWCK Atmel TWI serial EEPROM Slave 1 I²C RTC I²C LCD controller I²C temp. sensor Slave 2 Slave 3 Slave 4 Rp: Pull up value as given by the I²C Standard 23.6 I/O Lines Description Table 23-4. I/O Lines Description Pin Name Pin Description TWD Two-wire Serial Data Input/Output TWCK Two-wire Serial Clock Input/Output TWALM SMBus SMBALERT Input/Output 23.
ATUC64/128/256L3/4U 23.7.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TWIS, the TWIS will stop functioning and resume operation after the system wakes up from sleep mode. The TWIS is able to wake the system from sleep mode upon address match, see Section 23.8.8 on page 572. 23.7.3 Clocks The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager.
ATUC64/128/256L3/4U Figure 23-4. Transfer Format TWD TWCK Start 23.8.2 Address R/W Ack Data Ack Data Ack Stop Operation The TWIS has two modes of operation: • Slave transmitter mode • Slave receiver mode A master is a device which starts and stops a transfer and generates the TWCK clock. A slave is assigned an address and responds to requests from the master. These modes are described in the following chapters. Figure 23-5.
ATUC64/128/256L3/4U TTOUT: Prescaled clock cycles used to time SMBUS timeout TTIMEOUT. SUDAT: Non-prescaled clock cycles for data setup and hold count. Used to time TSU_DAT. EXP: Specifies the clock prescaler setting used for the SMBUS timeouts. Figure 23-6. Bus Timing Diagram t HIGH t LOW S t t LOW t HD:STA SU:DAT t HD:DAT t t SU:DAT t 23.8.2.2 SU:STA SU:STO P Sr Setting Up and Performing a Transfer Operation of the TWIS is mainly controlled by the Control Register (CR).
ATUC64/128/256L3/4U In I²C mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The General Call address is checked for address match if CR.GCMATCH is one. In SMBus mode: • The address in CR.ADR is checked for address match if CR.SMATCH is one. • The Alert Response Address is checked for address match if CR.SMAL is one. • The Default Address is checked for address match if CR.SMDA is one. • The Host Header Address is checked for address match if CR.SMHH is one. 23.8.2.
ATUC64/128/256L3/4U 4. NBYTES is updated. If CR.CUP is one, NBYTES is incremented, otherwise NBYTES is decremented. 5. After each data byte has been transmitted, the master transmits an ACK (Acknowledge) or NAK (Not Acknowledge) bit. If a NAK bit is received by the TWIS, the SR.NAK bit is set. Note that this is done two CLK_TWIS cycles after TWCK has been sampled by the TWIS to be HIGH (see Figure 23-9). The NAK indicates that the transfer is finished, and the TWIS will wait for a STOP or REPEATED START.
ATUC64/128/256L3/4U Figure 23-8. Slave Transmitter with Multiple Data Bytes TWD S DADR R A DATA n A DATA n+5 A DATA n+m N P TCOMP TXRDY STOP sent by master Write THR (Data n) NBYTES set to m Write THR (Data n+1) Write THR (Data n+m) Last data sent Figure 23-9. Timing Relationship between TWCK, SR.NAK, and SR.BTF TWD DATA (LSB) N P TWCK SR.NAK SR.BTF t1 t1 t1: (CLK_TWIS period) x 2 23.8.
ATUC64/128/256L3/4U slave to pull it down in order to generate the acknowledge. The master polls the data line during this clock pulse. The SR.RXRDY bit indicates that a data byte is available in the RHR. The RXRDY bit is also used as Receive Ready for the Peripheral DMA Controller receive channel. Figure 23-10. Slave Receiver with One Data Byte TWD S DADR W A DATA A P TCOMP RXRDY Read RHR Figure 23-11.
ATUC64/128/256L3/4U To assure correct behavior, respect the following programming sequences: 23.8.6.1 Data Transmit with the Peripheral DMA Controller 1. Initialize the transmit Peripheral DMA Controller (memory pointers, size, etc.). 2. Configure the TWIS (ADR, NBYTES, etc.). 3. Start the transfer by enabling the Peripheral DMA Controller to transmit. 4. Wait for the Peripheral DMA Controller end-of-transmit flag. 5. Disable the Peripheral DMA Controller. 23.8.6.
ATUC64/128/256L3/4U enabled when NBYTES reaches zero. NBYTES must therefore be set to the total number of data bytes in the transmission, including the PEC byte. 23.8.7.2 Timeouts The Timing Register (TR) configures the SMBus timeout values. If a timeout occurs, the slave will leave the bus. The SR.SMBTOUT bit is also set. 23.8.7.3 SMBALERT A slave can get the master’s attention by pulling the SMBALERT line low. This is done by writing a one to the SMBus Alert (SMBALERT) bit in CR.
ATUC64/128/256L3/4U Table 23-5. Bus Events Event Effect Start+Sadr on bus, current slave is addressed, corresponding address match enable bit in CR set, SR.STREN and SR.SOAM are set. Correct address match bit in SR is set. SR.TRA updated according to transfer direction (updating is done one CLK_TWIS cycle after address match bit is set). Slave stretches TWCK immediately after transmitting the address ACK bit. TWCK remains stretched until all address match bits in SR have been cleared.
ATUC64/128/256L3/4U 23.9 User Interface Table 23-6.
ATUC64/128/256L3/4U 23.9.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - TENBIT 23 22 21 20 19 18 17 16 ADR[9:8] ADR[7:0] 15 14 13 12 11 10 9 8 SODR SOAM CUP ACK PECEN SMHH SMDA SMBALERT 7 6 5 4 3 2 1 0 SWRST - - STREN GCMATCH SMATCH SMEN SEN • TENBIT: Ten Bit Address Match 0: Disables Ten Bit Address Match. 1: Enables Ten Bit Address Match.
ATUC64/128/256L3/4U • SWRST: Software Reset This bit will always read as 0. Writing a zero to this bit has no effect. Writing a one to this bit resets the TWIS. • STREN: Clock Stretch Enable 0: Disables clock stretching if RHR/THR buffer full/empty. May cause over/underrun. 1: Enables clock stretching if RHR/THR buffer full/empty. • GCMATCH: General Call Address Match 0: Causes the TWIS not to acknowledge the General Call Address. 1: Causes the TWIS to acknowledge the General Call Address.
ATUC64/128/256L3/4U 23.9.2 Name: NBYTES Register NBYTES Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 NBYTES • NBYTES: Number of Bytes to Transfer Writing to this field updates the NBYTES counter. The field can also be read to learn the progress of the transfer.
ATUC64/128/256L3/4U 23.9.3 Name: Timing Register TR Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 EXP 23 22 21 20 27 26 25 24 - - - - 19 18 17 16 11 10 9 8 3 2 1 0 SUDAT 15 14 13 12 TTOUT 7 6 5 4 TLOWS • EXP: Clock Prescaler Used to specify how to prescale the SMBus TLOWS counter.
ATUC64/128/256L3/4U 23.9.4 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data Byte When the RXRDY bit in the Status Register (SR) is one, this field contains a byte received from the TWI bus.
ATUC64/128/256L3/4U 23.9.5 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Data Byte to Transmit Write data to be transferred on the TWI bus here.
ATUC64/128/256L3/4U 23.9.6 Name: Packet Error Check Register PECR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 PEC • PEC: Calculated PEC Value The calculated PEC value. Updated automatically by hardware after each byte has been transferred. Reset by hardware after a STOP condition.
ATUC64/128/256L3/4U 23.9.7 Name: Status Register SR Access Type: Read-only Offset: 0x18 Reset Value: 0x000000002 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN TRA - TCOMP SEN TXRDY RXRDY • BTF: Byte Transfer Finished This bit is cleared when the corresponding bit in SCR is written to one.
ATUC64/128/256L3/4U • SMBPECERR: SMBus PEC Error This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus PEC error has occurred. • SMBTOUT: SMBus Timeout This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a SMBus timeout has occurred. • NAK: NAK Received This bit is cleared when the corresponding bit in SCR is written to one. This bit is set when a NAK was received from the master during slave transmitter operation.
ATUC64/128/256L3/4U 23.9.8 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 23.9.9 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 23.9.10 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - TXRDY RXRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 23.9.11 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 BTF REP STO SMBDAM SMBHHM SMBALERTM GCM SAM 15 14 13 12 11 10 9 8 - BUSERR SMBPECERR SMBTOUT - - - NAK 7 6 5 4 3 2 1 0 ORUN URUN - - TCOMP - - - Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 23.9.
ATUC64/128/256L3/4U 23.9.13 Name: Version Register (VR) VR Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION [11:8] 3 2 1 0 VERSION [7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 23.10 Module Configuration The specific configuration for each TWIS instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 23-7. Module Clock Name Module Name Clock Name Description TWIS0 CLK_TWIS0 Clock for the TWIS0 bus interface TWIS1 CLK_TWIS1 Clock for the TWIS1 bus interface Table 23-8.
ATUC64/128/256L3/4U 24. Inter-IC Sound Controller (IISC) Rev: 1.0.0.0 24.1 Features • Compliant with Inter-IC Sound (I2S) bus specification • Master, slave, and controller modes: • • • • • 24.
ATUC64/128/256L3/4U 24.3 Block Diagram Figure 24-1. IISC Block Diagram IISC Peripheral DMA Controller Interrupt Controller 24.4 Clocks PB clock PB Rx Tx IRQ Transmitter IWS ISDI ISDO I/O Lines Description Table 24-1. I/O Lines Description Pin Name 24.
ATUC64/128/256L3/4U 24.5.3 Clocks The clock for the IISC bus interface (CLK_IISC) is generated by the Power Manager. This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to disable the IISC before disabling the clock, to avoid freezing the IISC in an undefined state. One of the generic clocks is connected to the IISC. The generic clock (GCLK_IISC) can be set to a wide range of frequencies and clock sources. The GCLK_IISC must be enabled and configured before use.
ATUC64/128/256L3/4U The Transmitter can be operated by writing to the Transmitter Holding Register (RHR), whenever the Transmit Ready (TXRDY) bit in the Status Register (SR) is set. Successive values written to THR should correspond to the samples from the left and right audio channels for the successive frames. The Receive Ready and Transmit Ready bits can be polled by reading the Status Register. The IISC processor load can be reduced by enabling interrupt-driven operation.
ATUC64/128/256L3/4U 24.6.5 Serial Clock and Word Select Generation The generation of clocks in the IISC is described in Figure 24-3 on page 596. In Slave mode, the Serial Clock and Word Select Clock are driven by an external master. ISCK and IWS pins are inputs and no generic clock is required by the IISC. In Master mode, the user can configure the Master Clock, Serial Clock, and Word Select Clock through the Mode Register (MR).
ATUC64/128/256L3/4U Figure 24-3. IISC Clocks Generation CR.CKEN/CKDIS MR.IMCKMODE Clock enable GCLK_IISC IMCK pin output Clock divider MR.IMCKMODE 0 MR.IMCKFS MR.DATALENGTH 1 ISCK pin output CR.CKEN/CKDIS 0 ISCK pin input 1 Internal bit clock Clock enable Clock divider MR.MODE = SLAVE MR.DATALENGTH IWS pin output 0 IWS pin input 24.6.
ATUC64/128/256L3/4U Data words are right-justified in the RHR and THR registers. For 16-bit compact stereo, the left sample uses bits 15 through 0 and the right sample uses bits 31 through 16 of the same data word. For 8-bit compact stereo, the left sample uses bits 7 through 0 and the right sample uses bits 15 through 8 of the same data word. 24.6.
ATUC64/128/256L3/4U Figure 24-4. Interrupt Block Diagram IER Set IMR Clear IDR Transmitter TXRDY TXUR Interrupt Control IISC Interrupt Request Receiver RXRDY RXOR 24.7 IISC Application Examples The IISC can support several serial communication modes used in audio or high-speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the IISC are not listed here. Figure 24-5.
ATUC64/128/256L3/4U Figure 24-6. Codec Application Block Diagram IMCK ISCK IISC Master Clock Serial Clock EXTERNAL AUDIO CODEC Word Select IWS ISDO ISDI Serial Data Out Serial Data In Serial Clock Word Select Left Time Slot Right Time Slot Dstart Dend Serial Data Out Serial Data In Figure 24-7.
ATUC64/128/256L3/4U 24.8 User Interface Table 24-3.
ATUC64/128/256L3/4U 24.8.
ATUC64/128/256L3/4U 24.8.2 Name: Mode Register MR Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 IWS24 IMCKMODE 23 22 21 20 - - - 15 14 - 27 26 25 24 19 18 17 16 - - - - - 13 12 11 10 9 8 TXSAME TXDMA TXMONO RXLOOP RXDMA RXMONO 7 6 5 4 2 1 0 - - - - MODE IMCKFS 3 DATALENGTH The Mode Register should only be written when the IISC is stopped, in order to avoid unwanted glitches on the IWS, ISCK, and ISDO outputs.
ATUC64/128/256L3/4U Table 24-4.
ATUC64/128/256L3/4U 24.8.3 Name: Status Register SR Access Type: Read-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY TXEN - RXOR RXRDY RXEN TXURCH RXORCH • TXURCH: Transmit Underrun Channel This field is cleared when SCR.
ATUC64/128/256L3/4U 24.8.4 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 24.8.5 Name: Status Set Register SSR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 - - - - - - 7 6 5 4 3 2 1 0 - TXUR - - - RXOR - - TXURCH RXORCH Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in SR.
ATUC64/128/256L3/4U 24.8.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 24.8.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 24.8.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - TXUR TXRDY - - RXOR RXRDY - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 24.8.9 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RHR[31:24] 23 22 21 20 RHR[23:16] 15 14 13 12 RHR[15:8] 7 6 5 4 RHR[7:0] • RHR: Received Word This field is set by hardware to the last received data word. If MR.DATALENGTH specifies less than 32 bits, data shall be rightjustified into the RHR field.
ATUC64/128/256L3/4U 24.8.10 Name: Transmit Holding Register THR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 THR[31:24] 23 22 21 20 THR[23:16] 15 14 13 12 THR[15:8] 7 6 5 4 THR[7:0] • THR: Data Word to Be Transmitted Next data word to be transmitted after the current word if TXRDY is not set. If MR.DATALENGTH specifies less than 32 bits, data shall be right-justified into the THR field.
ATUC64/128/256L3/4U 24.8.11 Name: Module Version VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 1 0 VARIANT 11 10 VERSION[11:8] 3 2 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 24.8.12 Name: Module Parameters PARAMETER Access Type: Read-only Offset: 0x2C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - - Reserved. No functionality associated.
ATUC64/128/256L3/4U 24.9 Module configuration The specific configuration for each IISC instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 24-7. IISC Clocks Clock Name Description CLK_IISC Clock for the IISC bus interface GCLK The generic clock used for the IISC is GCLK6 Table 24-8.
ATUC64/128/256L3/4U 25. Pulse Width Modulation Controller (PWMA) Rev: 2.0.1.0 25.1 Features • Left-aligned non-inverted 12-bit PWM • Common 12-bit timebase counter • • • • • • • • 25.
ATUC64/128/256L3/4U 25.3 Block Diagram Figure 25-1. PWMA Block Diagram PB IRQ PB Clock Domain Control CLK_PWMA TCLR TOP READY Interrupt Handling CHERR SPREAD WAVEXOR Channel Select Duty Cycle Adjust Channel_0 Sync Spread Spectrum Counter GCLK Timebase Counter PWM Blocks Duty Cycle Register TOFL ETV COMP Channel 0 Channel 1 Channel m GCLK Domain CWG PWMA[m:0] 25.4 I/O Lines Description Each channel outputs one PWM waveform on one external I/O line. Table 25-1. 25.
ATUC64/128/256L3/4U 25.5.1 I/O Lines The pins used for interfacing the PWMA may be multiplexed with I/O Controller lines. The programmer must first program the I/O Controller to assign the desired PWMA pins to their peripheral function. It is only required to enable the PWMA outputs actually in use. 25.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the PWMA, the PWMA will stop functioning and resume operation after the system wakes up from sleep mode. 25.5.
ATUC64/128/256L3/4U SPREAD field of CR (CR.SPREAD) is zero). When the timebase counter reaches its effective top value, it restarts counting from zero. The period of the PWMA output waveform is then: T PWMA = ETV + 1 T GCLK The timebase counter can be reset by writing a one to the Timebase Clear bit in CR (CR.TCLR). Note that this can cause a glitch to the output PWM waveforms in use. 25.6.
ATUC64/128/256L3/4U When writing a one to CR.TCLR, the timebase counter and the spread spectrum counter are reset at their lower limit values and the effective top value of the timebase counter will also be reset. 25.6.4 Duty Cycle and Waveform Properties Each PWM channel has its own duty cycle value (DCV) which is write-only and cannot be read out. The duty cycle value can be changed in two approaches as described in Section25.6.6. When the duty cycle value is zero, the PWM output is zero.
ATUC64/128/256L3/4U (ISDUTY) register. Each channel has a corresponding enabling bit in the Interlinked Single Value Channel Set (ISCHSET) register(s). When a bit is written to one in the ISCHSET register, the duty cycle register for the corresponding channel will be updated with the value stored in the ISDUTY register. It can only be updated when the READY bit in the Status Register (SR.READY) is one, indicating that the PWMA is ready for writing. Figure 25-3 on page 620 shows the writing procedure.
ATUC64/128/256L3/4U 25.6.7 Open Drain Mode Some pins can be used in open drain mode, allowing the PWMA waveform to toggle between 0V and up to 5V on these pins. In this mode the PWMA will drive the pin to zero or leave the output open. An external pullup can be used to pull the pin up to the desired voltage. To enable open drain mode on a pin the PWMAOD function must be selected instead of the PWMA function in the I/O Controller.
ATUC64/128/256L3/4U the increase event will decrease the duty cycle value and decrease event will increase the duty cycle value. If both the increase event and the decrease event occur at the same time for a channel, the duty cycle value will not be changed. The number of channels supporting input peripheral events is device specific. Please refer to the Module Configuration section at the end of this chapter for details. 25.6.10.
ATUC64/128/256L3/4U 25.7 User Interface Table 25-3.
ATUC64/128/256L3/4U 25.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - SPREAD[8] 23 22 21 20 19 18 17 16 11 10 9 8 SPREAD[7:0] 15 14 13 12 TOP 7 6 5 4 3 2 1 0 - - - - - - TCLR EN • SPREAD: Spread Spectrum Limit Value The spread spectrum limit value, together with the TOP field, defines the range for the spread spectrum counter.
ATUC64/128/256L3/4U 25.7.2 Name: Interlinked Single Value Duty Register ISDUTY Access Type: Write-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 DUTY[11:8] 3 2 DUTY[7:0] • DUTY: Duty Cycle Value The duty cycle value written to this field is written simultaneously to all channels selected in the ISCHSETm register.
ATUC64/128/256L3/4U 25.7.
ATUC64/128/256L3/4U 25.7.4 Name: Interlinked Multiple Value Channel Select IMCHSEL Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SEL3 23 22 21 20 SEL2 15 14 13 12 SEL1 7 6 5 4 SEL0 • SELn: Channel Select The duty cycle of the PWMA channel SELn will be updated with the value stored in the DUTYn register when IMCHSEL is written. If SELn points to a non-implemented channel, the write will be discarded.
ATUC64/128/256L3/4U 25.7.5 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 25.7.6 Interrupt Disable Register Name: IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 25.7.7 Interrupt Mask Register Name: IMR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 25.7.8 Name: Status Register SR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - BUSY READY - TOFL • BUSY: Interface Busy This bit is automatically cleared when the interface is no longer busy.
ATUC64/128/256L3/4U 25.7.9 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 1 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - READY - TOFL Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 25.7.10 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x24 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 CHANNELS • CHANNELS: Channels Implemented This field contains the number of channels implemented on the device.
ATUC64/128/256L3/4U 25.7.11 Name: Version Register VERSION Access Type: Read-only Offset: 0x28 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 25.7.12 Name: Top Value Register TVR Access Type: Read/Write Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 TOP[11:8] 3 2 TOP[7:0] • TOP: Timebase Counter Top Value The top value for the timebase counter. The value written to the CR.
ATUC64/128/256L3/4U 25.7.13 Name: Interlinked Single Value Channel Set ISCHSETm Access Type: Write-only Offset: 0x30+m*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SET 23 22 21 20 SET 15 14 13 12 SET 7 6 5 4 SET • SET: Single Value Channel Set If the bit n in SET is one, the duty cycle of PWMA channel n will be updated with the value written to ISDUTY.
ATUC64/128/256L3/4U 25.7.14 Name: Channel Event Response Register CHERRm Access Type: Read/Write Offset: 0x34+m*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHER 23 22 21 20 CHER 15 14 13 12 CHER 7 6 5 4 CHER • CHER: Channel Event Response 0: The increase event will increase the duty cycle value by one in a PWM period for the corresponding channel and the decrease event will decrease the duty cycle value by one.
ATUC64/128/256L3/4U 25.7.15 Name: Channel Event Enable Register CHEERm Access Type: Read/Write Offset: 0x38+m*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CHEE 23 22 21 20 CHEE 15 14 13 12 CHEE 7 6 5 4 CHEE • CHEE: Channel Event Enable 0: The input peripheral event for the corresponding channel is disabled. 1: The input peripheral event for the corresponding channel is enabled.
ATUC64/128/256L3/4U 25.7.16 Name: Composite Waveform Generation CWG Access Type: Read/Write Offset: 0x3C+k*0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 XOR 23 22 21 20 XOR 15 14 13 12 XOR 7 6 5 4 XOR • XOR: Pair Waveform XOR’ed If the bit n in XOR field is one, the pair of PWMA output waveforms will be XORed before output. The even number output will be the XOR’ed output and the odd number output will be reverse of it.
ATUC64/128/256L3/4U 25.7.17 Name: Interlinked Multiple Value Duty0/1/2/3 Register DUTY0/1/2/3 Access Type: Write-only Offset: 0x80-0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 1 0 DUTY[11:8] 3 2 DUTY[7:0] These registers allows up to 4 channels to be updated with a common 12-bits duty cycle value at a time.
ATUC64/128/256L3/4U 25.8 Module Configuration The specific configuration for each PWMA instance is listed in the following tables. The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 25-4. PWMA Configuration Feature PWMA Number of PWM channels 36 Channels supporting incoming peripheral events 0, 6, 8, 9, 11, 14, 19, and 20 PWMA channels with Open Drain mode 21, 27, and 28 Table 25-5.
ATUC64/128/256L3/4U 26. Timer/Counter (TC) Rev: 2.2.3.1.3 26.1 Features • Three 16-bit Timer Counter channels • A wide range of functions including: • • • • 26.
ATUC64/128/256L3/4U 26.3 Block Diagram Figure 26-1.
ATUC64/128/256L3/4U When using the TIOA lines as inputs the user must make sure that no peripheral events are generated on the line. Refer to the Peripheral Event System chapter for details. 26.5.2 Power Management If the CPU enters a sleep mode that disables clocks used by the TC, the TC will stop functioning and resume operation after the system wakes up from sleep mode. 26.5.3 Clocks The clock for the TC bus interface (CLK_TC) is generated by the Power Manager.
ATUC64/128/256L3/4U The current value of the counter is accessible in real time by reading the Channel n Counter Value Register (CVn). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 26.6.1.
ATUC64/128/256L3/4U 26.6.1.4 Clock control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 26-3 on page 646. • The clock can be enabled or disabled by the user by writing to the Counter Clock Enable/Disable Command bits in the Channel n Clock Control Register (CCRn.CLKEN and CCRn.CLKDIS). In Capture mode it can be disabled by an RB load event if the Counter Clock Disable with RB Loading bit in CMRn is written to one (CMRn.
ATUC64/128/256L3/4U In Waveform mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 26.6.1.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode.
ATUC64/128/256L3/4U The RA Loading Selection field in CMRn (CMRn.LDRA) defines the TIOA edge for the loading of the RA register, and the RB Loading Selection field in CMRn (CMRn.LDRB) defines the TIOA edge for the loading of the RB register. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
32142D–06/2013 TIOA TIOB SYNC MTIOA MTIOB TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 1 Edge Detector ETRGEDG SWTRG CLKI S R OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP S R CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS SR Timer/Counter Channel If RA is not Loaded or RB is Loaded ABETRG BURST TCCLKS Compare RC = Register C COVFS INT ATUC64/128/256L3/4U
ATUC64/128/256L3/4U 26.6.3 Waveform Operating Mode Waveform operating mode is entered by writing a one to the CMRn.WAVE bit. In Waveform operating mode the TC channel generates one or two PWM signals with the same frequency and independently programmable duty cycles, or generates different types of oneshot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event.
32142D–06/2013 TIOB SYNC TIMER_CLOCK1 TIMER_CLOCK2 TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 XC0 XC1 XC2 EEVT Edge Detector EEVTEDG SWTRG ENETRG Trig CLK S R Register A Compare RC = CPCSTOP CPCDIS Compare RB = CLKDIS Register C R S CLKEN Register B Q CLKSTA Compare RA = OVF WAVSEL RESET 16-bit Counter WAVSEL Q SR Timer/Counter Channel 1 BURST CLKI CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC O utput Contr oller O utput Cont r oller TCCLKS TIOB MTIOB
ATUC64/128/256L3/4U 26.6.3.2 WAVSEL = 0 When CMRn.WAVSEL is zero, the value of CVn is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of CVn is reset. Incrementation of CVn starts again and the cycle continues. See Figure 26-6 on page 652. An external event trigger or a software trigger can reset the value of CVn. It is important to note that the trigger may occur at any time. See Figure 26-7 on page 653. RC Compare cannot be programmed to generate a trigger in this configuration.
ATUC64/128/256L3/4U Figure 26-7. WAVSEL= 0 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA 26.6.3.3 WAVSEL = 2 When CMRn.WAVSEL is two, the value of CVn is incremented from zero to the value of RC, then automatically reset on a RC Compare. Once the value of CVn has been reset, it is then incremented and so on. See Figure 26-8 on page 654.
ATUC64/128/256L3/4U Figure 26-8. WAVSEL = 2 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 26-9. WAVSEL = 2 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples Time TIOB TIOA 26.6.3.4 WAVSEL = 1 When CMRn.WAVSEL is one, the value of CVn is incremented from 0 to 0xFFFF.
ATUC64/128/256L3/4U A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-11 on page 655. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CMRn.CPCSTOP = 1) and/or disable the counter clock (CMRn.CPCDIS = 1). Figure 26-10.
ATUC64/128/256L3/4U 26.6.3.5 WAVSEL = 3 When CMRn.WAVSEL is three, the value of CVn is incremented from zero to RC. Once RC is reached, the value of CVn is decremented to zero, then re-incremented to RC and so on. See Figure 26-12 on page 656. A trigger such as an external event or a software trigger can modify CVn at any time. If a trigger occurs while CVn is incrementing, CVn then decrements. If a trigger is received while CVn is decrementing, CVn then increments. See Figure 26-13 on page 657.
ATUC64/128/256L3/4U Figure 26-13. WAVSEL = 3 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC Counter decremented by trigger RB Counter incremented by trigger RA Waveform Examples TIOB Time TIOA 26.6.3.6 External event/trigger conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The External Event Selection field in CMRn (CMRn.
ATUC64/128/256L3/4U • RB Compare Effect on TIOB (CMRn.BCPB) • RC Compare Effect on TIOA (CMRn.ACPC) • RA Compare Effect on TIOA (CMRn.
ATUC64/128/256L3/4U 26.7 User Interface Table 26-3.
ATUC64/128/256L3/4U Notes: 1. Read-only if CMRn.WAVE is zero. 2. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
ATUC64/128/256L3/4U 26.7.1 Name: Channel Control Register CCR Access Type: Write-only Offset: 0x00 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - SWTRG CLKDIS CLKEN • SWTRG: Software Trigger Command 1: Writing a one to this bit will perform a software trigger: the counter is reset and the clock is started.
ATUC64/128/256L3/4U 26.7.
ATUC64/128/256L3/4U 0: TIOB is used as an external trigger. • ETRGEDG: External Trigger Edge Selection ETRGEDG Edge 0 none 1 rising edge 2 falling edge 3 each edge • LDBDIS: Counter Clock Disable with RB Loading 1: Counter clock is disabled when RB loading occurs. 0: Counter clock is not disabled when RB loading occurs. • LDBSTOP: Counter Clock Stopped with RB Loading 1: Counter clock is stopped when RB loading occurs. 0: Counter clock is not stopped when RB loading occurs.
ATUC64/128/256L3/4U 26.7.
ATUC64/128/256L3/4U • BCPC: RC Compare Effect on TIOB BCPC Effect 0 none 1 set 2 clear 3 toggle • BCPB: RB Compare Effect on TIOB BCPB Effect 0 none 1 set 2 clear 3 toggle • ASWTRG: Software Trigger Effect on TIOA ASWTRG Effect 0 none 1 set 2 clear 3 toggle • AEEVT: External Event Effect on TIOA AEEVT Effect 0 none 1 set 2 clear 3 toggle • ACPC: RC Compare Effect on TIOA ACPC Effect 0 none 1 set 2 clear 3 toggle 665 32142D–06/2013
ATUC64/128/256L3/4U • ACPA: RA Compare Effect on TIOA ACPA Effect 0 none 1 set 2 clear 3 toggle • WAVE 1: Waveform mode is enabled. 0: Waveform mode is disabled (Capture mode is enabled).
ATUC64/128/256L3/4U • CPCSTOP: Counter Clock Stopped with RC Compare 1: Counter clock is stopped when counter reaches RC. 0: Counter clock is not stopped when counter reaches RC. • BURST: Burst Signal Selection BURST Burst Signal Selection 0 The clock is not gated by an external signal. 1 XC0 is ANDed with the selected clock. 2 XC1 is ANDed with the selected clock. 3 XC2 is ANDed with the selected clock. • CLKI: Clock Invert 1: Counter is incremented on falling edge of the clock.
ATUC64/128/256L3/4U 26.7.4 Name: Channel Counter Value Register CV Access Type: Read-only Offset: 0x10 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 CV[15:8] 7 6 5 4 CV[7:0] • CV: Counter Value CV contains the counter value in real time.
ATUC64/128/256L3/4U 26.7.5 Name: Channel Register A RA Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x14 + n * 0X40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RA[15:8] 7 6 5 4 RA[7:0] • RA: Register A RA contains the Register A value in real time.
ATUC64/128/256L3/4U 26.7.6 Name: Channel Register B RB Access Type: Read-only if CMRn.WAVE = 0, Read/Write if CMRn.WAVE = 1 Offset: 0x18 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RB[15:8] 7 6 5 4 RB[7:0] • RB: Register B RB contains the Register B value in real time.
ATUC64/128/256L3/4U 26.7.7 Name: Channel Register C RC Access Type: Read/Write Offset: 0x1C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 3 2 1 0 RC[15:8] 7 6 5 4 RC[7:0] • RC: Register C RC contains the Register C value in real time.
ATUC64/128/256L3/4U 26.7.8 Name: Channel Status Register SR Access Type: Read-only Offset: 0x20 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Note: Reading the Status Register will also clear the interrupt bit for the corresponding interrupts.
ATUC64/128/256L3/4U • CPBS: RB Compare Status 1: This bit is set when an RB Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • CPAS: RA Compare Status 1: This bit is set when an RA Compare has occurred and CMRn.WAVE is one. 0: This bit is cleared when the SR register is read. • LOVRS: Load Overrun Status 1: This bit is set when RA or RB have been loaded at least twice without any read of the corresponding register and CMRn.WAVE is zero.
ATUC64/128/256L3/4U 26.7.9 Name: Channel Interrupt Enable Register IER Access Type: Write-only Offset: 0x24 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 26.7.10 Name: Channel Interrupt Disable Register IDR Access Type: Write-only Offset: 0x28 + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 26.7.11 Name: Channel Interrupt Mask Register IMR Access Type: Read-only Offset: 0x2C + n * 0x40 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 26.7.12 Name: Block Control Register BCR Access Type: Write-only Offset: 0xC0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - SYNC • SYNC: Synchro Command 1: Writing a one to this bit asserts the SYNC signal which generates a software trigger simultaneously for each of the channels.
ATUC64/128/256L3/4U 26.7.
ATUC64/128/256L3/4U • TC0XC0S: External Clock Signal 0 Selection TC0XC0S Signal Connected to XC0 0 TCLK0 1 none 2 TIOA1 3 TIOA2 679 32142D–06/2013
ATUC64/128/256L3/4U 26.7.14 Name: Features Register FEATURES Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - BRPBHSB UPDNIMPL 7 6 5 4 3 2 1 0 CTRSIZE • BRPBHSB: Bridge type is PB to HSB 1: Bridge type is PB to HSB. 0: Bridge type is not PB to HSB. • UPDNIMPL: Up/down is implemented 1: Up/down counter capability is implemented.
ATUC64/128/256L3/4U 26.7.15 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 26.8 Module Configuration The specific configuration for each Timer/Counter instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 26-4. 26.8.
ATUC64/128/256L3/4U 27. Peripheral Event System Rev: 1.0.0.1 27.1 Features • • • • 27.2 Direct peripheral to peripheral communication system Allows peripherals to receive, react to, and send peripheral events without CPU intervention Cycle deterministic event communication Asynchronous interrupts allow advanced peripheral operation in low power sleep modes Overview Several peripheral modules can be configured to emit or respond to signals known as peripheral events.
ATUC64/128/256L3/4U Table 27-1.
ATUC64/128/256L3/4U Table 27-3. Peripheral Event Mapping from AST Generator Generated Event User Effect ACIFB Comparison is triggered if the ACIFB.CONFn register is written to 11 (Event Triggered Single Measurement Mode) and the EVENTEN bit in the ACIFB.CTRL register is written to 1. ADCIFB Conversion is triggered if the TRGMOD bit in the ADCIFB.TRGR register is written to 111 (Peripheral Event Trigger). CAT Trigger one iteration of autonomous touch detection.
ATUC64/128/256L3/4U tem will only be woken up if the user peripheral generates an interrupt as a result of the operation. This concept is known as SleepWalking and is described in further detail in the Power Manager chapter. Note that asynchronous peripheral events may be associated with a delay due to the need to restart the system clock source if this has been stopped in the sleep mode. 27.
ATUC64/128/256L3/4U 28. Audio Bit Stream DAC (ABDACB) Rev.: 1.0.0.0 28.1 Features • 16 bit digital stereo DAC • Oversampling D/A conversion architecture • • • • • • • 28.
ATUC64/128/256L3/4U 28.4 I/O Lines Description Table 28-1. 28.5 I/O Lines Description Pin Name Pin Description Type DAC[0] Output for channel 0 Output DACN[0] Inverted output for channel 0 Output DAC[1] Output for channel 1 Output DACN[1] Inverted output for channel 1 Output CLK Clock output for DAC Output Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 28.5.
ATUC64/128/256L3/4U 28.6 Functional Description 28.6.1 Construction The Audio Bitstream DAC is divided into several parts, the user interface, the signal processing blocks, and the Sigma Delta modulator blocks. See Figure 28-1 on page 687. The user interface is used to configure the signal processing blocks and to input new data samples to the converter.The signal processing blocks manages volume control, offset control, and upsampling.
ATUC64/128/256L3/4U 28.6.3 Basic operation To convert audio data to a digital bitstream the user must first initialize the ABDACB as described in Section 28.6.2. When the ABDACB is initialized and enabled it will indicate that it is ready to receive new data by setting the Transmit Ready bit in the Status Register (SR.TXRDY). When the TXRDY bit is set in the Status Register the user has to write new samples to Sample Data Register 0 (SDR0) and Sample Data Register 1 (SDR1).
ATUC64/128/256L3/4U Figure 28-2. Output signals with CMOC=0 Figure 28-3. Output signals with CMOC=1 28.6.7 Volume Control The Audio Bitstream DAC have two volume control registers, Volume Control Register 0 (VCR0) and Volume Control Register 1 (VCR1), that can be used to adjust the volume for the corresponding channel. The volume control is linear and will only scale each sample according to the value in the Volume Control (VOLUME) field in the volume control registers.
ATUC64/128/256L3/4U put of the DAC pins will have a voltage given by the following equation, given that it is configured to run at the default upsampling ratio of 128: 33- SDR ------------------------- V VDDIO ------------ VOLUME V OUT = 1 --- – --------15 15 2 128 2 2 –1 If one want to get coherence between the sign of the input data and the output voltage one can use the DATAN outputs or invert the sign of the input data by software. 28.6.
ATUC64/128/256L3/4U SDR1) before 1/FS second, or an underrun will occur, as indicated by the Underrun Interrupt bit in SR (SR.TXUR). The interrupt bits in SR are cleared by writing a one to the corresponding bit in the Status Clear Register (SCR). 28.6.12 Frequency Response Figure Figure 28-4 to Figure 28-7 show the frequency response for the system. The sampling frequency used is 48 kHz, but the response will be the same for other sampling frequencies, always having the first zero at FS. Figure 28-4.
ATUC64/128/256L3/4U Figure 28-5. Frequency Response up to Sampling Frequency Figure 28-6.
ATUC64/128/256L3/4U Figure 28-7.
ATUC64/128/256L3/4U 28.7 User Interface Table 28-2.
ATUC64/128/256L3/4U 28.7.1 Name: Control Register CR Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 23 - 22 - 21 - 20 - 19 - 15 - 14 - 13 - 12 - 7 SWRST 6 - 5 MONO 4 CMOC 26 25 24 18 17 DATAFORMAT 16 11 - 10 - 9 - 8 - 3 ALTUPR 2 - 1 SWAP 0 EN FS • FS: Sampling Frequency Must be set to the matching data sampling frequency, see Table 28-3. Table 28-3. Generic Clock Requirements CR.FS Description GCLK (CR.ALTUPR=1) GCLK (CR.
ATUC64/128/256L3/4U • DATAFORMAT: Data Word Format Table 28-4. Data Word Format DATAFORMAT Word length 0 32 bits 1 24 bits 2 20 bits 3 18 bits 4 16 bits 5 16 bits compact stereo 6 8 bits 7 8 bits compact stereo Comment Channel 1 sample in bits 31 through 16, channel 0 sample in bits 15 through 0 in SDR0 Channel 1 sample in bits 15 through 8, channel 0 sample in bits 7through 0 in SDR0 • SWRST: Software Reset Writing a zero to this bit does not have any effect.
ATUC64/128/256L3/4U 28.7.2 Name: Sample Data Register 0 SDR0 Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA: Sample Data Sample Data for channel 0 in two’s complement format. Data must be right-justified, see Table 28-5. Table 28-5.
ATUC64/128/256L3/4U 28.7.3 Name: Sample Data Register 1 SDR1 Access Type: Read/Write Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DATA[31:24] 23 22 21 20 DATA[23:16] 15 14 13 12 DATA[15:8] 7 6 5 4 DATA[7:0] • DATA: Sample Data Sample Data for channel 1 in two’s complement format. Data must be right-justified, see Table 28-5 on page 699.
ATUC64/128/256L3/4U 28.7.4 Name: Volume Control Register 0 VCR0 Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 MUTE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 13 12 11 VOLUME[14:8] 10 9 8 7 6 5 4 3 2 1 0 VOLUME[7:0] • MUTE: Mute 0: Channel 0 is not muted. 1: Channel 0 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 0.
ATUC64/128/256L3/4U 28.7.5 Name: Volume Control Register 1 VCR1 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 MUTE 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 13 12 11 VOLUME[14:8] 10 9 8 7 6 5 4 3 2 1 0 VOLUME[7:0] • MUTE: Mute 0: Channel 1 is not muted. 1: Channel 1 is muted. • VOLUME: Volume Control 15-bit value adjusting the volume for channel 1.
ATUC64/128/256L3/4U 28.7.6 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 28.7.7 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x18 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 28.7.8 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x1C Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. A bit in this register is cleared when the corresponding bit in IDR is written to one.
ATUC64/128/256L3/4U 28.7.9 Name: Status Register SR Access Type: Read-only Offset: 0x20 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 BUSY • TXUR: Transmit Underrun This bit is cleared when no underrun has occurred since the last time this bit was cleared (by reset or by writing to SCR).
ATUC64/128/256L3/4U 28.7.10 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 TXUR 1 TXRDY 0 - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in SR and the corresponding interrupt request.
ATUC64/128/256L3/4U 28.7.11 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 - 18 - 17 - 16 - 15 - 14 - 13 - 12 - 11 - 10 - 9 - 8 - 7 - 6 - 5 - 4 - 3 - 2 - 1 - 0 - Reserved. No functionality associated.
ATUC64/128/256L3/4U 28.7.12 Name: Version Register VERSION Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 31 - 30 - 29 - 28 - 27 - 26 - 25 - 24 - 23 - 22 - 21 - 20 - 19 18 17 16 15 - 14 - 13 - 12 - 11 10 9 VERSION[11:8] 8 7 6 5 4 3 2 0 VARIANT 1 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 28.8 Module Configuration The specific configuration for each ABDACB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 28-6. ABDACB Clocks Clock Name Description CLK_ABDACB Clock for the ABDACB bus interface GCLK The generic clock used for the ABDACB is GCLK6 Table 28-7.
ATUC64/128/256L3/4U 29. ADC Interface (ADCIFB) Rev:1.0.1.1 29.1 Features • Multi-channel Analog-to-Digital Converter with up to 12-bit resolution • Enhanced Resolution Mode • • • • • 29.
ATUC64/128/256L3/4U 29.3 Block Diagram Figure 29-1. ADCIFB Block Diagram ADCIFB I/O Controller TRIGGER ADP0 ADP1 Trigger Timer Resisitve Touch Screen Sequencer ADC Control Logic CLK_ADC CLK_ADCIFB User Interface Peripheral Bus AD1 AD2 ....
ATUC64/128/256L3/4U 29.4 I/O Lines Description Table 29-1. I/O Lines Description Pin Name Description Type ADVREFP Reference voltage Analog TRIGGER External trigger Digital ADP0 Drive Pin 0 for Resistive Touch Screen top channel (Xp) Digital ADP1 Drive Pin 1 for Resistive Touch Screen right channel (Yp) Digital AD0-ADn Analog input channels 0 to n Analog 29.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below.
ATUC64/128/256L3/4U 29.5.4 DMA The ADCIFB DMA handshake interface is connected to the Peripheral DMA Controller. Using the ADCIFB DMA functionality requires the Peripheral DMA Controller to be programmed first. 29.5.5 Interrupts The ADCIFB interrupt request line is connected to the interrupt controller. Using the ADCIFB interrupt request functionality requires the interrupt controller to be programmed first. 29.5.
ATUC64/128/256L3/4U To start converting data the user can either manually start a conversion sequence by writing a one to the START bit in the Control Register (CR.START) or configure an automatic trigger to initiate the conversions. The automatic trigger can be configured to trig on many different conditions. Refer to Section 29.8.1 for details. The result of the conversion is stored in the Last Converted Data Register (LCDR) as they become available, overwriting the result from the previous conversion.
ATUC64/128/256L3/4U 29.6.5 ADC Clock The ADCIFB generates an internal clock named CLK_ADC that is used by the Analog-to-Digital Converter cell to perform conversions. The CLK_ADC frequency is selected by writing to the PRESCAL field in the ADC Configuration Register (ACR). The CLK_ADC range is between CLK_ADCIFB/2, if PRESCAL is 0, and CLK_ADCIFB/128, if PRESCAL is 63 (0x3F).
ATUC64/128/256L3/4U Channels are enabled by writing a one to the corresponding bit in the Channel Enable Register (CHER), and disabled by writing a one to the corresponding bit in the Channel Disable Register (CHDR). Active channels are listed in the Channel Status Register (CHSR). When a conversion sequence is started, all enabled channels will be converted in one sequence and the result will be placed in the Last Converted Data Register (LCDR) with the channel number used to produce the result.
ATUC64/128/256L3/4U clear an active interrupt request, write a one to the corresponding bit in the Interrupt Clear Register (ICR). The source for the interrupt requests are the status bits in the Status Register (SR). The SR shows the ADCIFB status at the time the register is read. The Interrupt Status Register (ISR) shows the status since the last write to the Interrupt Clear Register.
ATUC64/128/256L3/4U 29.7.1 Resistive Touch Screen Principles A resistive touch screen is based on two resistive films, each one fitted with a pair of electrodes, placed at the top and bottom on one film, and on the right and left on the other. Between the two, there is a layer that acts as an insulator, but makes a connection when pressure is applied to the screen. This is illustrated in Figure 29-2 on page 719. Figure 29-2.
ATUC64/128/256L3/4U 29.7.3 Resistive Touch Screen Pin Connections Table 29-2. Resistive Touch Screen Pin Connections ADCIFB Pin TS Signal, APOE == 0 TS Signal, APOE == 1 ADP0 Xp through a resistor No Connect ADP1 Yp through a resistor No Connect ADtspo+0 Xp Xp ADtspo+1 Xm Xm ADtspo+2 Yp Yp ADtspo+3 Ym Ym The resistive touch screen film signals connects to the ADCIFB using the AD and ADP pins.
ATUC64/128/256L3/4U R filmy V AD tspo + 2 = --------------------------------------------- V DP 1 R filmy + R resistory The ADP pins are used by default, as the APOE bit is zero after reset. Writing a one to the APOE bit instructs the ADCIFB Resistive Touch Screen Sequencer to use the already connected ADtspo+0 and ADtspo+2 pins to drive VDD to XP and YP signals directly. In this mode the ADP pins can be used as general purpose I/O pins.
ATUC64/128/256L3/4U 29.7.4 Resistive Touch Screen Sequencer The Resistive Touch Screen Sequencer is responsible for applying voltage to the resistive touch screen films as described in Section 29.7.2. This is done by controlling the output enable and the output value of the ADP and AD pins. This allows the Resistive Touch Screen Sequencer to add a voltage gradient on one film while keeping the other film floating so a touch can be measured.
ATUC64/128/256L3/4U Figure 29-4. Resistive Touch Screen Pen Detect Resistive Touch Screen Sequencer XP GND XM GND YP Pullup YM Tristate T o the ADC PENDBC D ebouncer Pen Int er r upt The Resistive Touch Screen Pen Detect can be used to generate an ADCIFB interrupt request or it can be used to trig a conversion, so that a position can be measured as soon as a contact is detected.
ATUC64/128/256L3/4U 29.8 Operating Modes The ADCIFB features two operating modes, each defining a separate conversion sequence: • ADC Mode: At each trigger, all the enabled channels are converted. • Resistive Touch Screen Mode: At each trigger, all enabled channels plus the resistive touch screen channels are converted as described in Section 29.8.3.
ATUC64/128/256L3/4U screen inputs, are automatically activated. In addition, if any other channels are enabled, they will be converted before and after the resistive touch screen conversion. At each trigger, the following sequence is performed: 1. If ACR.SLEEP is one, wake up the ADC cell and wait for the startup time. 2. Convert all enabled channels before TSPO and store the results in the LCDR. 3. Apply supply on the inputs XP and XM during the Sample and Hold Time. 4.
ATUC64/128/256L3/4U 29.9 User Interface Table 29-3.
ATUC64/128/256L3/4U 29.9.1 Control Register Register Name: CR Access Type: Write-only Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - DIS EN 7 6 5 4 3 2 1 0 - - - - - - START SWRST • DIS: ADCDIFB Disable Writing a zero to this bit has no effect. Writing a one to this bit disables the ADCIFB.
ATUC64/128/256L3/4U 29.9.
ATUC64/128/256L3/4U 29.9.
ATUC64/128/256L3/4U 29.9.4 Name: Trigger Register TRGR Access Type: Read/Write Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 TRGPER[15:8] 23 22 21 20 TRGPER[7:0] 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - TRGMOD • TRGPER: Trigger Period Effective only if TRGMOD defines a Periodic Trigger.
ATUC64/128/256L3/4U 29.9.5 Name: Compare Value Register CVR Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 - - - - 23 22 21 20 27 26 25 24 HV[11:8] 19 18 17 16 11 10 9 8 1 0 HV[7:0] 15 14 13 12 - - - - 7 6 5 4 LV[11:8] 3 2 LV[7:0] • HV: High Value Defines the high value used when comparing analog input. • LV: Low Value Defines the low value used when comparing analog input.
ATUC64/128/256L3/4U 29.9.6 Name: Status Register SR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - EN 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY • EN: Enable Status 0: The ADCIFB is disabled. 1: The ADCIFB is enabled. This bit is cleared when CR.DIS is written to one.
ATUC64/128/256L3/4U This bit is set when pen contact is detected and pen detect is enabled. • OVRE: Overrun Error Status This bit is cleared when no Overrun Error has occurred since the start of a conversion sequence. This bit is set when one or more Overrun Error has occurred since the start of a conversion sequence. • DRDY: Data Ready Status 0: No data has been converted since the last reset. 1: One or more conversions have completed since the last reset and data is available in LCDR.
ATUC64/128/256L3/4U 29.9.7 Name: Interrupt Status Register ISR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY • CELSE: Compare Else Status This bit is cleared when the corresponding bit in ICR is written to one.
ATUC64/128/256L3/4U 29.9.8 Name: Interrupt Clear Register ICR Access Type: Write-only Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 29.9.9 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x20 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 29.9.10 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 29.9.11 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - CELSE CGT CLT - - BUSY READY 7 6 5 4 3 2 1 0 - - NOCNT PENCNT - - OVRE DRDY 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 29.9.12 Name: Last Converted Data Register LCDR Access Type: Read-only Offset: 0x2C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 11 10 9 8 1 0 LCCH 15 14 13 12 - - - - 7 6 5 4 LDATA[11:8] 3 2 LDATA[7:0] • LCCH: Last Converted Channel This field indicates what channel was last converted, i.e. what channel the LDATA represents.
ATUC64/128/256L3/4U 29.9.13 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHn: Channel n Implemented 0: The corresponding channel is not implemented.
ATUC64/128/256L3/4U 29.9.14 Name: Version Register VERSION Access Type: Read-only Offset: 0x34 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the Module. No functionality associated.
ATUC64/128/256L3/4U 29.9.
ATUC64/128/256L3/4U 29.9.
ATUC64/128/256L3/4U 29.9.17 Name: Channel Status Register CHSR Access Type: Read-only Offset: 0x48 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 CH31 CH30 CH29 CH28 CH27 CH26 CH25 CH24 23 22 21 20 19 18 17 16 CH23 CH22 CH21 CH20 CH19 CH18 CH17 CH16 15 14 13 12 11 10 9 8 CH15 CH14 CH13 CH12 CH11 CH10 CH9 CH8 7 6 5 4 3 2 1 0 CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0 • CHn: Channel N Status 0: The corresponding channel is disabled.
ATUC64/128/256L3/4U 29.10 Module Configuration The specific configuration for each ADCIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 29-5. Module Configuration Feature ADCIFB Number of ADC channels 9 (8 + 1 internal temperature sensor channel) Table 29-6. ADCIFB Clocks Clock Name Description CLK_ADCIFB Clock for the ADCIFB bus interface Table 29-7.
ATUC64/128/256L3/4U 30. Analog Comparator Interface (ACIFB) Rev: 2.0.2.2 30.1 Features • Controls an array of Analog Comparators • Low power option • • • • 30.
ATUC64/128/256L3/4U 30.3 Block Diagram Figure 30-1. ACIFB Block Diagram Analog Comparators ACIFB TR.ACTEST0 ACP0 Peripheral Bus CLK_ACIFB INP + ACOUT0 INN GCLK FILTER AC ACN0 INTERRUPT GENERATION CONF0.INSELN ……………... ACREFN ACPn IRQ PERIPHERAL EVENT GENERATION CTRL.ACTEST INP TRIGGER + ACOUTn INN EVENTS FILTER AC ACNn - CONFn.INSELN TR.ACTESTn 30.4 I/O Lines Description There are two groups of analog comparators, A and B, as shown in Table 30-1.
ATUC64/128/256L3/4U Table 30-2. I/O Line Description Pin Name Pin Description Type ACBPn Positive reference pin for Analog Comparator B n Analog ACBNn Negative reference pin for Analog Comparator B n Analog ACREFN Reference Voltage for all comparators selectable for INN Analog The signal names corresponds to the groups A and B of analog comparators. For normal mode, the mapping from input signal names in the block diagram to the signal names is given in Table 30-3. Table 30-3. 30.
ATUC64/128/256L3/4U 30.5.4 Interrupts The ACIFB interrupt request line is connected to the interrupt controller. Using the ACIFB interrupt requires the interrupt controller to be programmed first. 30.5.5 Peripheral Events The ACIFB peripheral events are connected via the Peripheral Event System. Refer to the Peripheral Event System chapter for details. 30.5.6 Debug Operation When an external debugger forces the CPU into debug mode, the ACIFB continues normal operation.
ATUC64/128/256L3/4U 30.6.1.2 User Triggered Single Measurement Mode In the UT mode, the user starts a single comparison by writing a one to the User Start Single Comparison bit (CTRL.USTART). This mode is enabled by writing CONFn.MODE to 2. After the startup time has passed, a single comparison is done and SR is updated. Appropriate peripheral events and interrupts are also generated. No new comparisons will be performed. CTRL.
ATUC64/128/256L3/4U • ACOUT = 1 if VINP > VINN • ACOUT = 0 if VINP < VINN • ACOUT = 0 if the AC output is not available (SR.ACRDY = 0) The output can optionally be filtered, as described in Section 30.6.6. 30.6.4.2 Normal Mode Interrupt The AC channels can generate interrupts. The Interrupt Settings field in the Configuration Register (CONFn.
ATUC64/128/256L3/4U Figure 30-2. Analog Comparator Interface in Window Mode ACAP0 + ACAN0 AC0 Filter - Interrupt Generator IRQ ACOUT0 ACWOUT COMMON Comparator pair 0 Window Module 30.6.5.1 - SR.ACCS0 ACBN0 Filter SR.WFCS0 AC1 window event ACOUT1 + ACBP0 Peripheral Event Generator Window Window Mode Output When operating in window mode, each channel generates the same ACOUT outputs as in normal mode, see Section 30.6.4.1.
ATUC64/128/256L3/4U 30.6.5.3 Window Mode Peripheral Events When operating in window mode, each channel can generate the same peripheral events as in normal mode, see Section 30.6.4.3. Additionally, when channels operate in window mode, programming Window Mode Event Selection Source (CONFWn.WEVSRC) can cause peripheral events to be generated when: • As soon as the common input voltage is inside the window. • As soon as the common input voltage is outside the window.
ATUC64/128/256L3/4U Figure 30-3. The Filtering Algorithm 2 FLEN 2 0 ”Result=0" Result = UNCHANGED HYS 30.7 ”Result=1" 2 FLEN HYS Peripheral Event Triggers Peripheral events from other modules can trigger comparisons in the ACIFB. All channels that are set up in Event Triggered Single Measurement Mode will be started simultaneously when a peripheral event is received.
ATUC64/128/256L3/4U 30.9 User Interface Table 30-4.
ATUC64/128/256L3/4U 30.9.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - 15 14 13 12 11 10 9 8 SUT[9:8] SUT[7:0] 7 6 5 4 3 2 1 0 ACTEST - ESTART USTART - - -EVENTEN EN • SUT: Startup Time SUT Analog Comparator startup time = ----------------- .
ATUC64/128/256L3/4U 30.9.
ATUC64/128/256L3/4U 30.9.3 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 30.9.4 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - WFINT3 WFINT2 WFINT1 WFINT0 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 SUTINT7 ACINT7 SUTINT6 ACINT6 SUTINT5 ACINT5 SUTINT4 ACINT4 7 6 5 4 3 2 1 0 SUTINT3 ACINT3 SUTINT2 ACINT2 SUTINT1 ACINT1 SUTINT0 ACINT0 Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 30.9.
ATUC64/128/256L3/4U 30.9.
ATUC64/128/256L3/4U 30.9.
ATUC64/128/256L3/4U 30.9.8 Name: Test Register TR Access Type: Read/Write Offset: 0x24 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACTEST7 ACTEST6 ACTEST5 ACTEST4 ACTEST3 ACTEST2 ACTEST1 ACTEST0 • ACTESTn: AC Output Override Value If CTRL.ACTEST is set, the ACn output is overridden with the value of ACTESTn.
ATUC64/128/256L3/4U 30.9.9 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x30 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - WIMPL3 WIMPL2 WIMPL1 WIMPL0 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 ACIMPL7 ACIMPL6 ACIMPL5 ACIMPL4 ACIMPL3 ACIMPL2 ACIMPL1 ACIMPL0 • WIMPLn: Window Pair n Implemented 0: Window Pair not implemented. 1: Window Pair implemented.
ATUC64/128/256L3/4U 30.9.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x34 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 30.9.11 Name: Window Configuration Register CONFWn Access Type: Read/Write Offset: 0x80,0x84,0x88,0x8C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - WFEN 15 14 13 12 11 10 9 8 - - - - WEVEN 7 6 5 4 3 2 - - - - - - WEVSRC 0 1 WIS • WFEN: Window Mode Enable 0: The window mode is disabled. 1: The window mode is enabled.
ATUC64/128/256L3/4U 30.9.12 Name: AC Configuration Register CONFn Access Type: Read/Write Offset: 0xD0,0xD4,0xD8,0xDC,0xE0,0xE4,0xE8,0xEC Reset Value: 0x00000000 31 30 - 29 28 27 26 FLEN 25 24 HYS 23 22 21 20 19 18 17 16 - - - - - - EVENP EVENN 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 - - MODE INSELP INSELN 3 2 - - 0 1 IS • FLEN: Filter Length 000: Filter off. n: Number of samples to be averaged =2n. • HYS: Hysteresis Value 0000: No hysteresis.
ATUC64/128/256L3/4U • IS: Interrupt Settings 00: Comparator interrupt when as VINP > VINN. 01: Comparator interrupt when as VINP < VINN. 10: Comparator interrupt on toggle of Analog Comparator output. 11: Comparator interrupt when comparison of VINP and VINN is done.
ATUC64/128/256L3/4U 30.10 Module Configuration The specific configuration for each ACIFB instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Refer to the Power Manager chapter for details. Table 30-5. ACIFB Configuration Feature ACIFB Number of channels 8 Table 30-6. ACIFB Clocks Clock Name Description CLK_ACIFB Clock for the ACIFB bus interface GCLK The generic clock used for the ACIFB is GCLK4 Table 30-7.
ATUC64/128/256L3/4U 31. Capacitive Touch Module (CAT) Rev: 4.0.0.0 31.1 Features • • • • • • 31.
ATUC64/128/256L3/4U 31.3 Block Diagram Figure 31-1. CAT Block Diagram Capacitive Touch Module (CAT) CLK_CAT Peripheral Bus Interface Registers Counters Finite State Machine Capacitor Charge and Discharge Sequence Generator GCLK_CAT CSAn CSBn I/O Controller Pins SMP VDIVEN NOTE: Italicized signals and blocks are used only for QMatrix operation DIS Discharge Current Sources Yn SYNC Peripheral Event System 31.
ATUC64/128/256L3/4U Table 31-1. 31.5 I/O Lines Description Name Description Type SMP SMP line (only used for QMatrix) SYNC Synchronize signal VDIVEN Voltage divider enable (only used for QMatrix) Output Input Output Product Dependencies In order to use the CAT module, other parts of the system must be configured correctly, as described below. 31.5.1 I/O Lines The CAT pins may be multiplexed with other peripherals.
ATUC64/128/256L3/4U Table 31-2. 31.5.
ATUC64/128/256L3/4U (MBLEN) when using the QMatrix acquisition method. Two additional handshakes support DMATouch by regulating transfers from memory to the DMATouch State Write Register (DMATSW) and from the DMATouch State Read Register (DMATSR) to memory. The Peripheral DMA Controller must be configured properly and enabled in order to perform direct memory access transfers to/from the CAT module. 31.5.
ATUC64/128/256L3/4U Figure 31-3. CAT Matrix Connections X2 X3 X6 QMatrix Sensor Array X7 YK0 Y0 Cs0 (Sense Capacitor) YK1 Y1 Cs1 (Sense Capacitor) AVR32 Chip Rsmp1 Rsmp0 SMP DIS Rdis VDIVEN Ra ACREFN Rb NOTE: If the CAT internal current sources will be enabled, the SMP signal and Rsmp resistors should NOT be included in the design. If the CAT internal current sources will NOT be enabled, the DIS signal and Rdis resistor should NOT be included in the design.
ATUC64/128/256L3/4U In order to use the QMatrix, QTouch group A, or QTouch group B acquisition capabilities, it is first necessary to set up the pin mode registers (PINMODE0, PINMODE1, and PINMODE2) and configuration registers (MGCFG0, MGCFG1, TGACFG0, TGACFG1, TGBCFG0, and TGBCFG1). The module must then be enabled using the CTRL register. In order to initiate acquisition, it is necessary to perform a write to the Acquisition Initiation and Selection Register (AISR).
ATUC64/128/256L3/4U The Y and YK pins remain clamped to ground apart from the specified number of burst pulses, when charge is transferred and captured into the sampling capacitor. 31.6.3 Capacitive Count Acquisition For the QMatrix, QTouch group A, and QTouch group B types of acquisition, the module acquires count values from the sensors, buffers them, and makes them available for reading in the ACOUNT register. Further processing of the count values must be performed by the CPU.
ATUC64/128/256L3/4U Figure 31-4. CAT Acquisition and Processing Sequence Idle AISR written flag set? No Yes Autonomous touch enabled (ATEN)? No 31.6.5 Acquire counts Yes Acquire autonomous touch count Wait for all acquired counts to be transferred Update autonomous touch detection algorithm Clear AISR written flag Spread Spectrum Sensor Drive To reduce electromagnetic compatibility issues, the capacitive sensors can be driven with a spread spectrum signal.
ATUC64/128/256L3/4U 9, 3, 4, 5, 6, 7, 8, 9, 3, 4, etc. MAXDEV must not exceed the value of (2(DIV+1)), or undefined behavior will occur. 31.6.6 Synchronization To prevent interference from the 50 or 60 Hz mains line the CAT can trigger acquisition on the SYNC signal. The SYNC signal should be derived from the mains line. The acquisition will trigger on a falling edge of this signal.
ATUC64/128/256L3/4U Problems with QMatrix acquisition of small sense capacitor voltages can be solved by connecting the negative reference pin (ACREFN) to a voltage divider that produces a small positive voltage (20 mV, typically) to cancel any negative input offset voltage. With a 3.3V supply, recommended values for the voltage divider are Ra (resistor from positive supply to ACREFN) of 8200 ohm and Rb (resistor from ACREFN to ground) of 50 ohm.
ATUC64/128/256L3/4U 31.7 User Interface Table 31-3.
ATUC64/128/256L3/4U Table 31-3.
ATUC64/128/256L3/4U 31.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 SWRST - - - - - - EN • SWRST: Software reset Writing a zero to this bit has no effect. Writing a one to this bit resets the module. The module will be disabled after the reset.
ATUC64/128/256L3/4U 31.7.2 Name: Autonomous Touch Pin Selection Register ATPINS Access Type: Read/Write Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - ATEN 7 6 5 4 3 2 1 0 - - - ATSP • ATEN: Autonomous Touch Enable 0: Autonomous QTouch acquisition and detection is disabled.
ATUC64/128/256L3/4U 31.7.3 Name: Pin Mode Registers 0, 1, and 2 PINMODE0, PINMODE1, and PINMODE2 Access Type: Read/Write Offset: 0x08, 0x0C, 0x74 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 SP[16] 12 11 10 9 8 3 2 1 0 SP[15:8] 7 6 5 4 SP[7:0] • SP: Sense Pair Mode Selection Each SP[n] bit determines the operation mode of sense pair n (CSAn and CSBn pins). The (PINMODE2.SP[n] PINMODE1.SP[n] PINMODE0.
ATUC64/128/256L3/4U 31.7.4 Name: Autonomous/DMA Touch Configuration Register 0 ATCFG0 Access Type: Read/Write Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 CHLEN 7 6 5 4 SELEN • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.
ATUC64/128/256L3/4U 31.7.5 Name: Autonomous/DMA Touch Configuration Register 1 ATCFG1 Access Type: Read/Write Offset: 0x14 Reset Value: 0x00000000 31 30 29 23 28 27 DISHIFT 22 21 26 - 20 25 24 SYNC SPREAD 19 18 17 16 11 10 9 8 3 2 1 0 DILEN 15 14 13 12 MAX[15:8] 7 6 5 4 MAX[7:0] • DISHIFT: Discharge Shift For the autonomous QTouch sensor and DMATouch sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time.
ATUC64/128/256L3/4U 31.7.6 Name: Autonomous/DMA Touch Configuration Register 2 ATCFG2 Access Type: Read/Write Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 15 14 FILTER 13 12 11 10 9 8 3 2 1 0 OUTSENS 7 6 5 4 SENSE • FILTER: Autonomous Touch Filter Setting For the autonomous QTouch sensor and DMATouch sensors, specifies how many positive detects in a row the CAT needs to have on the sensor before reporting it as a touch.
ATUC64/128/256L3/4U 31.7.7 Name: Autonomous/DMA Touch Configuration Register 3 ATCFG3 Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 PTHR 15 14 13 12 PDRIFT 7 6 5 4 NDRIFT • PTHR: Positive Recalibration Threshold For the autonomous QTouch sensor and DMATouch sensors, specifies how far a sensor’s signal must move in a positive direction from the reference in order to cause a recalibration.
ATUC64/128/256L3/4U 31.7.8 Name: Touch Group x Configuration Register 0 TGxCFG0 Access Type: Read/Write Offset: 0x20, 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 CHLEN 7 6 5 4 SELEN • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 1 MHz to produce the sampling clock.
ATUC64/128/256L3/4U 31.7.9 Name: Touch Group x Configuration Register 1 TGxCFG1 Access Type: Read/Write Offset: 0x24, 0x2C Reset Value: 0x00000000 31 30 - - 23 22 29 28 DISHIFT 21 20 27 26 25 24 - - SYNC SPREAD 19 18 17 16 11 10 9 8 3 2 1 0 DILEN 15 14 13 12 MAX[15:8] 7 6 5 4 MAX[7:0] • DISHIFT: Discharge Shift For the sensors in QTouch group x, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time.
ATUC64/128/256L3/4U 31.7.10 Name: Matrix Group Configuration Register 0 MGCFG0 Access Type: Read/Write Offset: 0x30 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 DIV[15:8] 23 22 21 20 DIV[7:0] 15 14 13 12 CHLEN 7 6 5 4 SELEN • DIV: Clock Divider The prescaler is used to ensure that the CLK_CAT clock is divided to around 4 MHz to produce the burst timing clock.
ATUC64/128/256L3/4U 31.7.11 Name: Matrix Group Configuration Register 1 MGCFG1 Access Type: Read/Write Offset: 0x34 Reset Value: 0x00000000 31 30 29 23 28 27 DISHIFT 22 21 26 - 20 25 24 SYNC SPREAD 19 18 17 16 11 10 9 8 3 2 1 0 DILEN 15 14 13 12 MAX[15:8] 7 6 5 4 MAX[7:0] • DISHIFT: Discharge Shift For QMatrix sensors, specifies how many bits the DILEN field should be shifted before using it to determine the discharge time.
ATUC64/128/256L3/4U 31.7.12 Name: Matrix Group Configuration Register 2 MGCFG2 Access Type: Read/Write Offset: 0x38 Reset Value: 0x00000000 31 30 29 ACCTRL 23 28 27 26 CONSEN 22 21 25 24 20 19 18 17 16 11 10 9 8 CXDILEN 15 14 13 12 7 6 SYNCTIM[11:8] 5 4 3 2 1 0 SYNCTIM[7:0] • ACCTRL: Analog Comparator Control When written to one, allows the CAT to disable the analog comparators when they are not needed. When written to zero, the analog comparators are always enabled.
ATUC64/128/256L3/4U 31.7.13 Name: Status Register SR Access Type: Read-only Offset: 0x3C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - DMATSR DMATSW 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - MBLREQ ATSTATE ATSC ATCAL ENABLED • DMATSC: DMATouch Sensor State Change 0: No change in the DMATSS register.
ATUC64/128/256L3/4U • ATCAL: Autonomous Touch Calibration Ongoing 0: The autonomous QTouch sensor is not calibrating. 1: The autonomous QTouch sensor is calibrating. • ENABLED: Module Enabled 0: The module is disabled. 1: The module is enabled.
ATUC64/128/256L3/4U 31.7.14 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x40 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 31.7.15 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x44 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 31.7.16 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x48 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 31.7.17 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x4C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 DMATSC - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - ACQDONE ACREADY 7 6 5 4 3 2 1 0 - - - - - ATSC ATCAL - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 31.7.18 Name: Acquisition Initiation and Selection Register AISR Access Type: Read/Write Offset: 0x50 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 - 7 6 5 4 - ACQSEL • ACQSEL: Acquisition Type Selection A write to this register initiates an acquisition of the following type: 00: QTouch Group A. 01: QTouch Group B. 10: QMatrix Group. 11: Undefined behavior.
ATUC64/128/256L3/4U 31.7.19 Name: Acquired Count Register ACOUNT Access Type: Read-only Offset: 0x54 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 Y 23 22 21 20 SPORX 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • Y: Y index The Y index (for QMatrix method) associated with this count value. • SPORX: Sensor pair or X index The sensor pair index (for QTouch method) or X index (for QMatrix method) associated with this count value.
ATUC64/128/256L3/4U 31.7.20 Name: Matrix Burst Length Register MBLEN Access Type: Write-only Offset: 0x58 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 BURST0 23 22 21 20 BURST1 15 14 13 12 BURST2 7 6 5 4 BURST3 • BURSTx: Burst Length x For QMatrix sensors, specifies how many times the switching sequence should be repeated before acquisition begins for each channel.
ATUC64/128/256L3/4U 31.7.21 Name: Discharge Current Source Register DICS Access Type: Read/Write Offset: 0x5C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 FSOURCES[7:0] 23 22 21 20 19 18 17 16 GLEN - - - - - INTVREFSEL INTREFSEL 15 14 13 12 11 10 9 8 - - - 7 6 5 1 0 TRIM 4 3 2 SOURCES[7:0] • FSOURCES: Force Discharge Current Sources When FSOURCES[n] is 0, the corresponding discharge current source behavior depends on SOURCES[n].
ATUC64/128/256L3/4U 31.7.
ATUC64/128/256L3/4U 31.7.23 Name: CSA Resistor Control Register CSARES Access Type: Read/Write Offset: 0x64 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 RES[16] 12 11 10 9 8 3 2 1 0 RES[15:8] 7 6 5 4 RES[7:0] • RES: Resistive Drive Enable When RES[n] is 0, CSA[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSA[n] has a nominal output resistance of 1kOhm during the burst phase.
ATUC64/128/256L3/4U 31.7.24 Name: CSB Resistor Control Register CSBRES Access Type: Read/Write Offset: 0x68 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 23 22 21 20 - 15 14 13 RES[16] 12 11 10 9 8 3 2 1 0 RES[15:8] 7 6 5 4 RES[7:0] • RES: Resistive Drive Enable When RES[n] is 0, CSB[n] has the same drive properties as normal I/O pads. When RES[n] is 1, CSB[n] has a nominal output resistance of 1kOhm during the burst phase.
ATUC64/128/256L3/4U 31.7.25 Name: Autonomous Touch Base Count Register ATBASE Access Type: Read-only Offset: 0x6C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • COUNT: Count value The base count currently stored by the autonomous touch sensor. This is useful for autonomous touch debugging purposes.
ATUC64/128/256L3/4U 31.7.26 Name: Autonomous Touch Current Count Register ATCURR Access Type: Read-only Offset: 0x70 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 23 22 21 20 - 15 14 13 12 COUNT[15:8] 7 6 5 4 COUNT[7:0] • COUNT: Count value The current count acquired by the autonomous touch sensor. This is useful for autonomous touch debugging purposes.
ATUC64/128/256L3/4U 31.7.27 Name: DMATouch State Write Register DMATSW Access Type: Write-only Offset: 0x78 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 10 9 8 2 1 0 DETCNT[23:16] 15 14 13 12 11 BASECNT[15:8] 7 6 5 4 3 BASECNT[7:0] • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm.
ATUC64/128/256L3/4U 31.7.28 Name: DMA Touch State Read Register DMATSR Access Type: Read/Write Offset: 0x7C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - NOTINCAL 23 22 21 20 19 18 17 16 10 9 8 2 1 0 DETCNT[23:16] 15 14 13 12 11 BASECNT[15:8] 7 6 5 4 3 BASECNT[7:0] • NOTINCAL: Not in Calibration Mode 0: Calibration should be performed on the next iteration of the DMATouch algorithm.
ATUC64/128/256L3/4U 31.7.29 Name: Analog Comparator Shift Offset Register x ACSHIx Access Type: Read/Write Offset: 0x80, 0x84, 0x88, 0x8C, 0x90, 0x94, 0x98, and 0x9C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 1 0 23 22 21 20 - 15 14 13 12 7 6 SHIVAL[11:8] 5 4 3 2 SHIVAL[7:0] • SHIVAL: Shift Offset Value Specifies the amount to shift the count value from each comparator. This allows the offset of each comparator to be compensated.
ATUC64/128/256L3/4U 31.7.30 Name: DMATouch Sensor Status Register DMATSS Access Type: Read-only Offset: 0xA0 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SS[31:24] 23 22 21 20 SS[23:16] 15 14 13 12 SS[15:8] 7 6 5 4 SS[7:0] • SS: Sensor Status 0: The DMATouch sensor is not active, i.e. the button is currently not pushed. 1: The DMATouch sensor is active, i.e. the button is currently pushed.
ATUC64/128/256L3/4U 31.7.31 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0xF8 Reset Value: - 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 SP[31:24] 23 22 21 20 SP[23:16] 15 14 13 12 SP[15:8] 7 6 5 4 SP[7:0] • SP[n]: Sensor pair implemented 0: The corresponding sensor pair is not implemented 1: The corresponding sensor pair is implemented.
ATUC64/128/256L3/4U 31.7.32 Name: Version Register VERSION Access Type: Read-only Offset: 0xFC Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant number Reserved. No functionality associated. • VERSION: Version number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 31.8 Module Configuration The specific configuration the CAT module is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 31-4. Feature CAT Number of touch sensors/Size of matrix Allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced. Table 31-5.
ATUC64/128/256L3/4U 32. Glue Logic Controller (GLOC) Rev: 1.0.0.0 32.1 Features • • • • 32.2 Glue logic for general purpose PCB design Programmable lookup table Up to four inputs supported per lookup table Optional filtering of output Overview The Glue Logic Controller (GLOC) contains programmable logic which can be connected to the device pins. This allows the user to eliminate logic gates for simple glue logic functions on the PCB. The GLOC consists of a number of lookup table (LUT) units.
ATUC64/128/256L3/4U 32.4 I/O Lines Description Table 32-1. I/O Lines Description Pin Name Pin Description Type IN0-INm Inputs to lookup tables Input OUT0-OUTn Output from lookup tables Output Each LUT have 4 inputs and one output. The inputs and outputs for the LUTs are mapped sequentially to the inputs and outputs. This means that LUT0 is connected to IN0 to IN3 and OUT0. LUT1 is connected to IN4 to IN7 and OUT1. In general, LUTn is connected to IN[4n] to IN[4n+3] and OUTn. 32.
ATUC64/128/256L3/4U 32.6.2 Configuring the Lookup Table The lookup table in each LUT unit can generate any logic expression OUT as a function of up to four inputs, IN[3:0]. The truth table for the expression is written to the TRUTH register for the LUT. Table 32-2 shows the truth table for LUT0. The truth table for LUTn is written to TRUTHn, and the corresponding input and outputs will be IN[4n] to IN[4n+3] and OUTn. Table 32-2. 32.6.
ATUC64/128/256L3/4U 32.7 User Interface Table 32-3. GLOC Register Memory Map Offset Register Register Name Access Reset 0x00+n*0x08 Control Register n CRn Read/Write 0x00000000 0x04+n*0x08 Truth Table Register n TRUTHn Read/Write 0x00000000 0x38 Parameter Register PARAMETER Read-only - (1) 0x3C Version Register VERSION Read-only - (1) Note: 1. The reset values are device specific. Please refer to the Module Configuration section at the end of this chapter.
ATUC64/128/256L3/4U 32.7.1 Name: Control Register n CRn Access Type: Read/Write Offset: 0x00+n*0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 FILTEN - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - AEN • FILTEN: Filter Enable 1: The output is glitch filtered 0: The output is not glitch filtered • AEN: Enable IN Inputs Input IN[n] is enabled when AEN[n] is one.
ATUC64/128/256L3/4U 32.7.
ATUC64/128/256L3/4U 32.7.3 Name: Parameter Register PARAMETER Access Type: Read-only Offset: 0x38 Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 LUTS • LUTS: Lookup Table Units Implemented This field contains the number of lookup table units implemented in this device.
ATUC64/128/256L3/4U 32.7.4 Name: VERSION Register VERSION Access Type: Read-only Offset: 0x3C Reset Value: - 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - 15 14 13 12 9 8 - - - - 7 6 5 4 VARIANT 11 10 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VARIANT: Variant Number Reserved. No functionality associated. • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 32.8 Module Configuration The specific configuration for each GLOC instance is listed in the following tables.The GLOC bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 32-4. GLOC Configuration Feature GLOC Number of LUT units 2 Table 32-5. GLOC Clocks Clock Name Description CLK_GLOC Clock for the GLOC bus interface GCLK The generic clock used for the GLOC is GCLK5 Table 32-6.
ATUC64/128/256L3/4U 33. aWire UART (AW) Rev: 2.3.0.0 33.1 Features • Asynchronous receiver or transmitter when the aWire system is not used for debugging. • One- or two-pin operation supported. 33.2 Overview If the AW is not used for debugging, the aWire UART can be used by the user to send or receive data with one start bit, eight data bits, no parity bits, and one stop bit. This can be controlled through the aWire UART user interface. This chapter only describes the aWire UART user interface.
ATUC64/128/256L3/4U 33.4 I/O Lines Description Table 33-1. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin. Input/Output 33.5 Product Dependencies In order to use this module, other parts of the system must be configured correctly, as described below. 33.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin.
ATUC64/128/256L3/4U 33.6.1 How to Initialize The Module To initialize the aWire UART user interface the user must first enable the clock by writing a one to the Clock Enable bit in the Clock Request Register (CLKR.CLKEN) and wait for the Clock Enable bit in the Status Register (SR.CENABLED) to be set. After doing this either receive, transmit or receive with resync must be selected by writing the corresponding value into the Mode field of the Control (CTRL.MODE) Register.
ATUC64/128/256L3/4U 33.6.6 Interrupts To make the CPU able to do other things while waiting for the aWire UART user interface to finish its operations the aWire UART user interface supports generating interrupts. All status bits in the Status Register can be used as interrupt sources, except the SR.BUSY and SR.CENABLED bits. To enable an interrupt the user must write a one to the corresponding bit in the Interrupt Enable Register (IER).
ATUC64/128/256L3/4U 33.7 User Interface Table 33-2.
ATUC64/128/256L3/4U 33.7.1 Name: Control Register CTRL Access Type: Read/Write Offset: 0x00 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - MODE • MODE: aWire UART user interface mode Table 33-3. aWire UART user interface Modes MODE Mode Description 0 Disabled 1 Receive 2 Transmit 3 Receive with resync.
ATUC64/128/256L3/4U 33.7.2 Name: Status Register SR Access Type: Read-only Offset: 0x04 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - CENABLED - BUSY • TRMIS: Transmit Mismatch 0: No transfers mismatches. 1: The transceiver was active when receiving.
ATUC64/128/256L3/4U This bit is set when the clock is disabled. This bit is cleared when the clock is enabled. • BUSY: Synchronizer Busy 0: The asynchronous interface is ready to accept more data. 1: The asynchronous interface is busy and will block writes to CTRL, BRR, and THR. This bit is set when the asynchronous interface becomes busy. This bit is cleared when the asynchronous interface becomes ready.
ATUC64/128/256L3/4U 33.7.3 Name: Status Clear Register SCR Access Type: Write-only Offset: 0x08 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect.
ATUC64/128/256L3/4U 33.7.4 Name: Interrupt Enable Register IER Access Type: Write-only Offset: 0x0C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will set the corresponding bit in IMR.
ATUC64/128/256L3/4U 33.7.5 Name: Interrupt Disable Register IDR Access Type: Write-only Offset: 0x10 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - Writing a zero to a bit in this register has no effect. Writing a one to a bit in this register will clear the corresponding bit in IMR.
ATUC64/128/256L3/4U 33.7.6 Name: Interrupt Mask Register IMR Access Type: Read-only Offset: 0x14 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - TRMIS - - OVERRUN DREADYINT READYINT 7 6 5 4 3 2 1 0 - - - - - - - - 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled.
ATUC64/128/256L3/4U 33.7.7 Name: Receive Holding Register RHR Access Type: Read-only Offset: 0x18 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Received Data The last byte received.
ATUC64/128/256L3/4U 33.7.8 Name: Transmit Holding Register THR Access Type: Read/Write Offset: 0x1C Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Transmit Data The data to send.
ATUC64/128/256L3/4U 33.7.
ATUC64/128/256L3/4U 33.7.10 Name: Version Register VERSION Access Type: Read-only Offset: 0x24 Reset Value: 0x00000200 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - 7 6 5 4 VERSION[11:8] 3 2 1 0 VERSION[7:0] • VERSION: Version Number Version number of the module. No functionality associated.
ATUC64/128/256L3/4U 33.7.11 Name: Clock Request Register CLKR Access Type: Read/Write Offset: 0x28 Reset Value: 0x00000000 31 30 29 28 27 26 25 24 - - - - - - - - 23 22 21 20 19 18 17 16 - - - - - - - - 15 14 13 12 11 10 9 8 - - - - - - - - 7 6 5 4 3 2 1 0 - - - - - - - CLKEN • CLKEN: Clock Enable 0: The aWire clock is disabled. 1: The aWire clock is enabled. Writing a zero to this bit will disable the aWire clock.
ATUC64/128/256L3/4U 33.8 Module Configuration The specific configuration for each aWire instance is listed in the following tables.The module bus clocks listed here are connected to the system bus clocks. Please refer to the Power Manager chapter for details. Table 33-4. AW Clocks Clock Name Description CLK_AW Clock for the AW bus interface Table 33-5.
ATUC64/128/256L3/4U 34. Programming and Debugging 34.1 Overview The ATUC64/128/256L3/4U supports programming and debugging through two interfaces, JTAG or aWire. JTAG is an industry standard interface and allows boundary scan for PCB testing, as well as daisy-chaining of multiple devices on the PCB. aWire is an Atmel proprietary protocol which offers higher throughput and robust communication, and does not require application pins to be reserved.
ATUC64/128/256L3/4U Table 34-1. 34.2.2 SAB Slaves, Addresses and Descriptions Slave Address [35:32] Description HSB 0x5 Alternative mapping for HSB space, for compatibility with other 32-bit AVR devices. Memory Service Unit 0x6 Memory Service Unit registers Reserved Other Unused SAB Security Restrictions The Service Access bus can be restricted by internal security measures. A short description of the security measures are found in the table below. 34.2.2.
ATUC64/128/256L3/4U Table 34-4. Security Bit SAB Restrictions Name Address start Address end Access OCD DCCPU, OCD DCEMU, OCD DCSR 0x100000110 0x100000118 Read/Write User page 0x580800000 0x581000000 Read Other accesses - - Table 34-5.
ATUC64/128/256L3/4U 34.3 On-Chip Debug Rev: 2.1.2.0 34.3.1 Features • • • • • • • • 34.3.2 Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.
ATUC64/128/256L3/4U selectable by OCD Registers, minimizing the chance that the AUX port will need to be shared with an application. Table 34-6. 34.3.
ATUC64/128/256L3/4U 34.3.5 Block Diagram Figure 34-1. On-Chip Debug Block Diagram aWire JTAG aWire JTAG AUX On-Chip Debug Memory Service Unit Service Access Bus Transmit Queue Watchpoints Debug PC Debug Instruction Breakpoints CPU 34.3.6 Program Trace Internal SRAM HSB Bus Matrix Data Trace Ownership Trace Memories and peripherals SAB-based Debug Features A debugger can control all OCD features by writing OCD registers over the SAB interface.
ATUC64/128/256L3/4U Figure 34-2. JTAG-based Debugger PC JTA G -based debug tool 10-pin ID C JTAG 32-bit A V R Figure 34-3. aWire-based Debugger PC aWire-based debug tool aWire 32-bit AVR 34.3.6.1 Debug Communication Channel The Debug Communication Channel (DCC) consists of a pair OCD registers with associated handshake logic, accessible to both CPU and debugger. The registers can be used to exchange data between the CPU and the debugmaster, both runtime as well as in debug mode.
ATUC64/128/256L3/4U The OCD system can generate an interrupt to the CPU when DCCPU is read and when DCEMU is written. This enables the user to build a custum debug protocol using only these registers. The DCCPU and DCEMU registers are available even when the security bit in the flash is active. For more information refer to the AVR32UC Technical Reference Manual. 34.3.6.2 Breakpoints One of the most fundamental debug features is the ability to halt the CPU, to examine registers and the state of the system.
ATUC64/128/256L3/4U 34.3.7.1 Cyclic Redundancy Check (CRC) The MSU can be used to automatically calculate the CRC of a block of data in memory. The MSU will then read out each word in the specified memory block and report the CRC32-value in an MSU register. 34.3.7.2 NanoTrace The MSU additionally supports NanoTrace. This is a 32-bit AVR-specific feature, in which trace data is output to memory instead of the AUX port.
ATUC64/128/256L3/4U Figure 34-4. AUX+JTAG Based Debugger PC T ra c e b u ffe r A U X +JTA G d e b u g to o l M ic t o r 3 8 AUX h ig h s p e e d JTA G AVR32 34.3.8.1 Trace Operation Trace features are enabled by writing OCD registers by the debugger. The OCD extracts the trace information from the CPU, compresses this information and formats it into variable-length messages according to the Nexus standard.
ATUC64/128/256L3/4U nels, each of which are controlled by a pair of OCD registers which determine the range of addresses (or single address) which should produce data trace messages. 34.3.8.4 Ownership Trace Program and data trace operate on virtual addresses. In cases where an operating system runs several processes in overlapping virtual memory segments, the Ownership Trace feature can be used to identify the process switch.
ATUC64/128/256L3/4U 34.4 JTAG and Boundary-scan (JTAG) Rev: 2.2.2.4 34.4.1 Features • IEEE1149.1 compliant JTAG Interface • Boundary-scan Chain for board-level testing • Direct memory access and programming capabilities through JTAG Interface 34.4.2 Overview The JTAG Interface offers a four pin programming and debug solution, including boundary-scan support for board-level testing. Figure 34-5 on page 856 shows how the JTAG is connected in an 32-bit AVR device.
ATUC64/128/256L3/4U 34.4.3 Block Diagram Figure 34-5. JTAG and Boundary-scan Access 32-bit AVR device JTAG JTAG master Boundary scan enable TAP Controller TDO TDI JTAG Pins TMS TCK TCK TMS TDI TDO Instruction register scan enable Data register scan enable Instruction Register TMS TCK TDO TDI JTAG data registers 2nd JTAG device Device Identification Register Boundary Scan Chain Pins and analog blocks By-pass Register Reset Register Part specific registers ...
ATUC64/128/256L3/4U 34.4.5.1 I/O Lines The TMS, TDI, TDO, and TCK pins are multiplexed with I/O lines. When the JTAG is used the associated pins must be enabled. To enable the JTAG pins, refer to Section 34.4.7. While using the multiplexed JTAG lines all normal peripheral activity on these lines is disabled. The user must make sure that no external peripheral is blocking the JTAG lines while debugging. 34.4.5.
ATUC64/128/256L3/4U Figure 34-6.
ATUC64/128/256L3/4U 34.4.7 How to Initialize the Module To enable the JTAG pins the TCK pin must be held low while the RESET_N pin is released. After enabling the JTAG interface the halt bit is set automatically to prevent the system from running code after the interface is enabled. To make the CPU run again set halt to zero using the HALT command.. JTAG operation when RESET_N is pulled low is not possible.
ATUC64/128/256L3/4U of TCK. In order to remain in the Shift-DR state, the TMS input must be held low. While the Data Register is shifted in from the TDI pin, the parallel inputs to the Data Register captured in the Capture-DR state is shifted out on the TDO pin. Apply the TMS sequence 1, 1, 0 to re-enter the Run-Test/Idle state. If the selected Data Register has a latched parallel-output, the latching takes place in the Update-DR state.
ATUC64/128/256L3/4U which is linked to the JTAG through a bus master module, which also handles synchronization between the TCK and SAB clocks. For more information about the SAB and a list of SAB slaves see the Service Access Bus chapter. 34.4.11.1 SAB Address Mode The MEMORY_SIZED_ACCESS instruction allows a sized read or write to any 36-bit address on the bus.
ATUC64/128/256L3/4U continue shifting the same instruction until the busy bit clears, or start shifting data. If shifting data, you must be prepared that the data shift may also report busy. • During Shift-DR of an address: The new address is ignored. The SAB stays in address mode, so no data must be shifted. Repeat the address until the busy bit clears. • During Shift-DR of read data: The read data is invalid. The SAB stays in data mode. Repeat scanning until the busy bit clears.
ATUC64/128/256L3/4U • Perform a CHIP_ERASE to clear the security bit. NOTE: This will erase all the contents of the non-volatile memory. 34.5 JTAG Instruction Summary The implemented JTAG instructions in the 32-bit AVR are shown in the table below. Table 34-8. Instruction OPCODE JTAG Instruction Summary Instruction Description 0x01 IDCODE Select the 32-bit Device Identification register as data register.
ATUC64/128/256L3/4U Note that the security bit will read as programmed and block these instructions also if the Flash Controller is statically reset. Other security mechanisms can also restrict these functions. If such mechanisms are present they are listed in the SAB address map section. 34.5.1.1 Notation Table 34-10 on page 864 shows bit patterns to be shifted in a format like "peb01". Each character corresponds to one bit, and eight bits are grouped together for readability.
ATUC64/128/256L3/4U Table 34-10. Instruction Description (Continued) 34.5.2 Instruction Description DR Size Shows the number of bits in the data register chain when this instruction is active. Example: 34 bits DR input value Shows which bit pattern to shift into the data register in the Shift-DR state when this instruction is active. Multiple such lines may exist, e.g., to distinguish between reads and writes.
ATUC64/128/256L3/4U 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Capture-DR: The Data on the external pins are sampled into the boundary-scan chain. 7. In Shift-DR: The boundary-scan chain is shifted by the TCK input. 8. Return to Run-Test/Idle. Table 34-12. SAMPLE_PRELOAD Details 34.5.2.
ATUC64/128/256L3/4U 34.5.2.4 INTEST This instruction selects the boundary-scan chain as Data Register for testing internal logic in the device. The logic inputs are determined by the boundary-scan chain, and the logic outputs are captured by the boundary-scan chain. The device output pins are driven from the boundary-scan chain. Starting in Run-Test/Idle, the INTEST instruction is accessed the following way: 1. Select the IR Scan path. 2.
ATUC64/128/256L3/4U 9. Return to Run-Test/Idle. Table 34-15. CLAMP Details 34.5.2.6 Instructions Details IR input value 00110 (0x06) IR output value p0001 DR Size 1 DR input value x DR output value x BYPASS This instruction selects the 1-bit Bypass Register as Data Register. Starting in Run-Test/Idle, the CLAMP instruction is accessed the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3.
ATUC64/128/256L3/4U Starting in Run-Test/Idle, OCD registers are accessed in the following way: 1. Select the IR Scan path. 2. In Capture-IR: The IR output value is latched into the shift register. 3. In Shift-IR: The instruction register is shifted by the TCK input. 4. Return to Run-Test/Idle. 5. Select the DR Scan path. 6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the OCD register. 7. Go to Update-DR and re-enter Select-DR Scan. 8.
ATUC64/128/256L3/4U 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a write operation, scan in the new contents of the register. 9. Return to Run-Test/Idle. For any operation, the full 7 bits of the address must be provided. For write operations, 32 data bits must be provided, or the result will be undefined. For read operations, shifting may be terminated once the required number of bits have been acquired.
ATUC64/128/256L3/4U The size field is encoded as i Table 34-19. Table 34-19.
ATUC64/128/256L3/4U Table 34-20. MEMORY_SIZED_ACCESS Details (Continued) 34.5.3.4 Instructions Details DR output value (Address phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb DR output value (Data read phase) xxxxxeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_WORD_ACCESS This instruction allows access to the entire Service Access Bus data area.
ATUC64/128/256L3/4U Table 34-21. MEMORY_WORD_ACCESS Details (Continued) 34.5.3.5 Instructions Details DR output value (Address phase) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xeb DR output value (Data read phase) xeb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xxx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb MEMORY_BLOCK_ACCESS This instruction allows access to the entire SAB data area.
ATUC64/128/256L3/4U Table 34-22. MEMORY_BLOCK_ACCESS Details (Continued) Instructions Details DR input value (Data write phase) dddddddd dddddddd dddddddd dddddddd xx DR output value (Data read phase) eb dddddddd dddddddd dddddddd dddddddd DR output value (Data write phase) xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb The overhead using block word access is 4 cycles per 32 bits of data, resulting in an 88% transfer efficiency, or 2.1 MBytes per second with a 20 MHz TCK frequency. 34.5.3.
ATUC64/128/256L3/4U 6. Scan in an 16-bit counter value. 7. Go to Update-DR and re-enter Select-DR Scan. 8. In Shift-DR: Scan out the busy bit, and until the busy bit clears goto 7. 9. Calculate an approximation to the internal clock speed using the elapsed time and the counter value. 10. Return to Run-Test/Idle. The full 16-bit counter value must be provided when starting the synch operation, or the result will be undefined.
ATUC64/128/256L3/4U Table 34-25. AVR_RESET Details (Continued) 34.5.3.9 Instructions Details DR Size Device specific. DR input value Device specific. DR output value Device specific. CHIP_ERASE This instruction allows a programmer to completely erase all nonvolatile memories in a chip. This will also clear any security bits that are set, so the device can be accessed normally. In devices without non-volatile memories this instruction does nothing, and appears to complete immediately.
ATUC64/128/256L3/4U 6. In Shift-DR: Scan in the value 1 to halt the CPU, 0 to start CPU execution. 7. Return to Run-Test/Idle. Table 34-27.
ATUC64/128/256L3/4U 34.5.4 JTAG Data Registers The following device specific registers can be selected as JTAG scan chain depending on the instruction loaded in the JTAG Instruction Register. Additional registers exist, but are implicitly described in the functional description of the relevant instructions. 34.5.4.1 Device Identification Register The Device Identification Register contains a unique identifier for each product.
ATUC64/128/256L3/4U System 34.5.4.3 Resets the whole chip, except the JTAG itself. Boundary--scan Chain The boundary-scan chain has the capability of driving and observing the logic levels on the digital I/O pins, as well as driving and observing the logic levels between the digital I/O pins and the internal logic. Typically, output value, output enable, and input data are all available in the boundary-scan chain.
ATUC64/128/256L3/4U 34.6 aWire Debug Interface (AW) Rev.: 2.3.0.1 34.6.1 Features • • • • • • • • 34.6.2 Single pin debug system. Half Duplex asynchronous communication (UART compatible). Full duplex mode for direct UART connection. Compatible with JTAG functionality, except boundary scan. Failsafe packet-oriented protocol. Read and write on-chip memory and program on-chip flash and fuses through SAB interface. On-Chip Debug access through SAB interface.
ATUC64/128/256L3/4U 34.6.3 Block Diagram Figure 34-8. aWire Debug Interface Block Diagram PB aWire Debug Interface Flash Controller CHIP_ERASE command AW User Interface CPU HALT command RESET command Power Manager External reset AW_ENABLE AW CONTROL Reset filter RESET_N Baudrate Detector SAB interface UART RW SZ ADDR DATA CRC SAB 34.6.4 I/O Lines Description Table 34-29. I/O Lines Description Name Description Type DATA aWire data multiplexed with the RESET_N pin.
ATUC64/128/256L3/4U 34.6.5.1 I/O Lines The pin used by AW is multiplexed with the RESET_N pin. The reset functionality is the default function of this pin. To enable the aWire functionality on the RESET_N pin the user must enable the AW either by sending the enable sequence over the RESET_N pin from an external aWire master or by enabling the aWire user interface. In 2-pin mode data is received on the RESET_N line, but transmitted on the DATAOUT line.
ATUC64/128/256L3/4U Table 34-30. aWire Packet Format Field Number of bytes Description 2 The number of bytes in the DATA field. Yes DATA LENGTH Data according to command/ response. Yes CRC 2 CRC calculated with the FCS16 polynomial. LENGTH Comment Optional CRC value of 0x0000 makes the aWire disregard the CRC if the master does not support it. No CRC calculation The CRC is calculated from the command/response, length, and data fields.
ATUC64/128/256L3/4U Avoiding drive contention when changing direction The aWire debug protocol uses one dataline in both directions. To avoid both the master and the slave to drive this line when changing direction the AW has a built in guard time before it starts to drive the line. At reset this guard time is set to maximum (128 bit cycles), but can be lowered by the master upon command. The AW will release the line immediately after the stop character has been transmitted.
ATUC64/128/256L3/4U 34.6.6.5 Resetting the AW The aWire master can reset the AW slave by pulling the RESET_N pin low for 20 ms. This is equivalent to disabling and then enabling AW. 34.6.6.6 2-pin Mode To avoid using special hardware when using a normal UART device as aWire master, the aWire slave has a 2-pin mode where one pin is used as input and on pin is used as output. To enable this mode the 2_PIN_MODE command must be sent.
ATUC64/128/256L3/4U 3f aw f sab = ---------------CV – 3 SAB Address Mode The Service Access Bus uses 36 address bits to address memory or registers in any of the slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses must have the lowest address bit cleared, and word accesses must have the two lowest address bits cleared.
ATUC64/128/256L3/4U 34.6.7 aWire Command Summary The implemented aWire commands are shown in the table below. The responses from the AW are listed in Section 34.6.8. Table 34-31. aWire Command Summary COMMAND Instruction Description 0x01 AYA “Are you alive”. 0x02 JTAG_ID Asks AW to return the JTAG IDCODE. 0x03 STATUS_REQUEST Request a status message from the AW. 0x04 TUNE Tell the AW to report the current baud rate.
ATUC64/128/256L3/4U 34.6.7.2 JTAG_ID This command instructs the AW to output the JTAG idcode in the following response. Table 34-34. JTAG_ID Details 34.6.7.3 Command Details Command value 0x02 Additional data N/A Possible responses 0xC0: IDCODE (Section 34.6.8.3) 0x41: NACK (Section 34.6.8.2) STATUS_REQUEST Asks the AW for a status message. Table 34-35. STATUS_REQUEST Details 34.6.7.
ATUC64/128/256L3/4U the Chip Erase ongoing bit in the status bytes received after the STATUS_REQUEST command. Table 34-38. CHIP_ERASE Details 34.6.7.7 Command Details Command value 0x06 Additional data N/A Possible responses 0x40: ACK (Section 34.6.8.1) 0x41: NACK (Section 34.6.8.2) DISABLE Disables the AW. The AW will respond with an ACK response and then disable itself. Table 34-39. DISABLE Details 34.6.7.
ATUC64/128/256L3/4U The 4 MSB of the 36 bit SAB address are submitted together with the size field (2 bits). Then follows the 4 remaining address bytes and finally the data bytes. The size of the transfer is specified using the values from the following table: Table 34-41. Size Field Decoding Size field Description 00 Byte transfer 01 Halfword transfer 10 Word transfer 11 Reserved Below is an example write command: 1. 0x55 (sync) 2. 0x80 (command) 3. 0x00 (length MSB) 4. 0x09 (length LSB) 5.
ATUC64/128/256L3/4U 1. The size of the data field: 7 (size and starting address + read length indicator) in the length field. 2. The size of the transfer: Words, halfwords, or bytes. 3. The starting address of the transfer. 4. The number of bytes to read (max 65532). The 4 MSB of the 36 bit SAB address are submitted together with the size field (2 bits). The 4 remaining address bytes are submitted before the number of bytes to read.
ATUC64/128/256L3/4U 34.6.7.11 HALT This command tells the CPU to halt code execution for safe programming. If the CPU is not halted during programming it can start executing partially loaded programs. To halt the processor, the aWire master should send 0x01 in the data field of the command. After programming the halting can be released by sending 0x00 in the data field of the command. Table 34-45. HALT Details 34.6.7.
ATUC64/128/256L3/4U 34.6.8 aWire Response Summary The implemented aWire responses are shown in the table below. Table 34-48. aWire Response Summary RESPONSE Instruction Description 0x40 ACK Acknowledge. 0x41 NACK Not acknowledge. Sent after CRC errors and after unknown commands. 0xC0 IDCODE The JTAG idcode. 0xC1 MEMDATA Values read from memory. 0xC2 MEMORY_READWRITE_STATUS Status after a MEMORY_WRITE or a MEMORY_READ command. OK, busy, error. 0xC3 BAUD_RATE The current baudrate.
ATUC64/128/256L3/4U 1. 0x55 (sync) 2. 0xC1 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0xCA (Data MSB) 6. 0xFE 7. 0xBA 8. 0xBE (Data LSB) 9. 0x00 (Status byte) 10. 0x00 (Bytes remaining MSB) 11. 0x00 (Bytes remaining LSB) 12. 0xXX (CRC MSB) 13. 0xXX (CRC LSB) The status is 0x00 and all data read are valid. An unsuccessful four byte read can look like this: 1. 0x55 (sync) 2. 0xC1 (command) 3. 0x00 (length MSB) 4. 0x07 (length LSB) 5. 0xCA (Data MSB) 6. 0xFE 7. 0xXX (An error has occurred.
ATUC64/128/256L3/4U 34.6.8.5 MEMORY_READWRITE_STATUS After a MEMORY_WRITE command this response is sent by AW. The response can also be sent after a MEMORY_READ command if AW encountered an error when receiving the address. The response contains 3 bytes, where the first is the status of the command and the 2 next contains the byte count when the first error occurred. The first byte is encoded this way: Table 34-54.
ATUC64/128/256L3/4U Table 34-58. STATUS_INFO Details 34.6.8.8 Response Details Response value 0xC4 Additional data 2 status bytes MEMORY_SPEED Counts the number of RC120M clock cycles it takes to sync one message to the SAB interface and back again. The SAB clock speed ( f sab ) can be calculated using the following formula: 3f aw f sab = ---------------CV – 3 Table 34-59. MEMORY_SPEED Details 34.6.
ATUC64/128/256L3/4U 35. Electrical Characteristics 35.1 Absolute Maximum Ratings* Table 35-1. Absolute Maximum Ratings Operating temperature..................................... -40C to +85C *NOTICE: Storage temperature...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.3V to VVDD(2)+0.3V Voltage on 5V tolerant(1) pins with respect to ground ............... .......
ATUC64/128/256L3/4U Table 35-3. Supply Rise Rates and Order(1) Rise Rate Symbol Parameter Min Max Unit VVDDIO DC supply peripheral I/Os 0 2.5 V/µs VVDDIN DC supply peripheral I/Os and internal regulator 0.002 2.5 V/µs Slower rise time requires external power-on reset circuit. VVDDCORE DC supply core 0 2.5 V/µs Rise before or at the same time as VDDIO VVDDANA Analog supply voltage 0 2.5 V/µs Rise together with VDDCORE Note: 35.3 Comment 1.
ATUC64/128/256L3/4U – VVDDCORE = 1.62V, supplied by the internal regulator – Corresponds to the 3.3V supply mode with 1.8V regulated I/O lines, please refer to the Supply and Startup Considerations section for more details • Equivalent to the 3.3V single supply mode • Consumption in 1.8V single supply mode can be estimated by subtracting the regulator static current • Operating conditions, external core supply (Figure 35-2) - used only when noted – VVDDIN = VVDDCORE = 1.8V – Corresponds to the 1.
ATUC64/128/256L3/4U Table 35-5. Mode Power Consumption for Different Operating Modes Conditions Active(1) Measured on Consumption Typ CPU running a recursive Fibonacci algorithm 300 CPU running a division algorithm 174 Idle(1) 96 (1) (1) 46 Stop 38 DeepStop 25 -OSC32K and AST stopped -Internal core supply Static Shutdown Note: µA/MHz 57 Frozen Standby Unit Amp0 14 µA -OSC32K running -AST running at 1KHz -External core supply (Figure 35-2) 7.
ATUC64/128/256L3/4U Figure 35-2.
ATUC64/128/256L3/4U 35.5 I/O Pin Characteristics Table 35-6.
ATUC64/128/256L3/4U Table 35-7. Symbol RPULLUP High-drive I/O Pin Characteristics(1) Parameter Pull-up resistance Condition Min Typ Max PA06 30 50 110 PA02, PB01, RESET 75 100 145 PA08, PA09 10 20 45 VVDD = 3.0V -0.3 0.3 * VVDD VVDD = 1.62V -0.3 0.3 * VVDD VVDD = 3.6V 0.7 * VVDD VVDD + 0.3 VVDD = 1.98V 0.7 * VVDD VVDD + 0.
ATUC64/128/256L3/4U 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-8.
ATUC64/128/256L3/4U Table 35-9. TWI Pin Characteristics(1) Symbol Parameter Condition VOL Output low-level voltage IOL = 3mA ILEAK Input leakage current Pull-up resistors disabled IIL Input low leakage 1 IIH Input high leakage 1 Input capacitance CIN tFALL Fall time Max frequency fMAX Min Typ Max Units 0.4 V 1 TQFP48 package 3.8 QFN48 package 3.5 TLLGA48 package 3.5 TQFP64 package 3.9 QFN64 package 3.5 Cbus = 400pF, VVDD > 2.0V 250 Cbus = 400pF, VVDD > 1.
ATUC64/128/256L3/4U can be found in the crystal datasheet. The capacitance of the external capacitors (CLEXT) can then be computed as follows: C LEXT = 2 C L – C i – C PCB where CPCB is the capacitance of the PCB and Ci is the internal equivalent load capacitance. Table 35-11. Crystal Oscillator Characteristics Symbol Parameter fOUT Crystal oscillator frequency(3) CL Crystal load capacitance(3) Ci Internal equivalent load capacitance tSTARTUP Startup time Min Typ Max Unit 0.
ATUC64/128/256L3/4U 35.6.2 32KHz Crystal Oscillator (OSC32K) Characteristics Figure 35-3 and the equation above also applies to the 32KHz oscillator connection. The user must choose a crystal oscillator where the crystal load capacitance CL is within the range given in the table. The exact value of CL can then be found in the crystal datasheet. Table 35-12.
ATUC64/128/256L3/4U 35.6.4 Digital Frequency Locked Loop (DFLL) Characteristics Table 35-14. Digital Frequency Locked Loop Characteristics Symbol Parameter Conditions (2) fOUT Output frequency fREF Reference frequency(2) FINE resolution step FINE > 100, all COARSE values (3) Frequency drift over voltage and temperature Open loop mode Accuracy(2) IDFLL Power consumption tSTARTUP Startup time(2) tLOCK Lock time Notes: Min Typ Max Unit 20 150 MHz 8 150 kHz 0.
ATUC64/128/256L3/4U Figure 35-4. DFLL Open Loop Frequency Variation(1)(2) DFLL Open Loop Frequency variation 160 150 Frequencies (MHz) 140 130 1,98V 120 1,8V 1.62V 110 100 90 80 -40 -20 0 20 40 60 80 Tem pera ture Notes: 1. The plot shows a typical open loop mode behavior with COARSE= 99 and FINE= 255. 2. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production.
ATUC64/128/256L3/4U 35.6.6 32kHz RC Oscillator (RC32K) Characteristics Table 35-16. 32kHz RC Oscillator Characteristics Symbol Parameter Conditions (1) Min Typ Max Unit 20 32 44 kHz fOUT Output frequency IRC32K Current consumption 0.7 µA tSTARTUP Startup time(1) 100 µs Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. 35.6.
ATUC64/128/256L3/4U Table 35-20. Flash Endurance and Data Retention Symbol Parameter NFARRAY Array endurance (write/page) 100k NFFUSE General Purpose fuses endurance (write/bit) 10k tRET Data retention 15 35.8 Conditions Min Typ Max Unit cycles years ABDACB Electrical Characteristics. Table 35-21. ABDACB Electrical Characteristics Symbol Parameter Conditions MIN Resolution TYP 16 Dynamic range (1)(2)(3) Unit Bits FS = 48.000kHz > 76 dB (1)(2)(3) SNR FS = 48.
ATUC64/128/256L3/4U 35.9 Analog Characteristics 35.9.1 Voltage Regulator Characteristics Table 35-22. VREG Electrical Characteristics Symbol Parameter Condition VVDDIN Input voltage range VVDDCORE Output voltage, calibrated value Typ Max 1.98 3.3 3.6 Units V Output voltage accuracy (1) IOUT DC output current(1) IVREG Static current of internal regulator Note: Min VVDDIN >= 1.98V 1.8 IOUT = 0.1mA to 60mA, VVDDIN > 1.98V 2 IOUT = 0.1mA to 60mA, VVDDIN <1.
ATUC64/128/256L3/4U 35.9.2 Power-on Reset 18 Characteristics Table 35-24. POR18 Characteristics Symbol Parameter VPOT+ Voltage threshold on VVDDCORE rising VPOT- Voltage threshold on VVDDCORE falling tDET Detection time(1) IPOR18 Current consumption tSTARTUP Note: Condition Min Typ Max 1.45 1.58 Units V 1.2 Time with VDDCORE < VPOTnecessary to generate a reset signal (1) Startup time 1.32 460 µs 4 µA 6 µs 1.
ATUC64/128/256L3/4U 35.9.3 Power-on Reset 33 Characteristics Table 35-25. POR33 Characteristics Symbol Parameter VPOT+ Voltage threshold on VVDDIN rising VPOT- Voltage threshold on VVDDIN falling tDET Detection time(1) IPOR33 Current consumption tSTARTUP Note: Condition Min Typ Max 1.49 1.58 Units V 1.3 Time with VDDIN < VPOTnecessary to generate a reset signal (1) Startup time 1.45 460 µs 20 µA 400 µs 1.
ATUC64/128/256L3/4U 35.9.4 Brown Out Detector Characteristics The values in Table 35-26 describe the values of the BODLEVEL in the flash General Purpose Fuse register. Table 35-26. BODLEVEL Values BODLEVEL Value Min Typ 011111 binary (31) 0x1F 1.60 100111 binary (39) 0x27 1.69 Max Units V Table 35-27.
ATUC64/128/256L3/4U 35.9.6 Analog to Digital Converter Characteristics Table 35-29. ADC Characteristics Symbol fADC Parameter Conditions ADC clock frequency Typ 6 10-bit resolution mode 6 8-bit resolution mode 6 Startup time Return from Idle Mode tCONV Conversion time (latency) fADC = 6MHz 15 11 VVDD > 3.0V, fADC = 6MHz, 12-bit resolution mode, low impedance source 28 VVDD > 3.0V, fADC = 6MHz, 10-bit resolution mode, low impedance source 460 VVDD > 3.
ATUC64/128/256L3/4U ( C SOURCE ) of the PCB and source must be taken into account when calculating the required sample and hold time. Figure 35-8 shows the ADC input channel equivalent circuit. Figure 35-8. ADC Input RSOURCE Positive Input RONCHIP CSOURCE VIN CONCHIP ADCVREFP/2 The minimum sample and hold time (in ns) can be found using this formula: t SAMPLEHOLD R ONCHIP + R SOURCE C ONCHIP + C SOURCE ln 2 n+1 Where n is the number of bits in the conversion.
ATUC64/128/256L3/4U Note: 1. These values are based on simulation and characterization of other AVR microcontrollers manufactured in the same process technology. These values are not covered by test limits in production. Table 35-33. Transfer Characteristics, 8-bit Resolution Mode(1) Parameter Conditions Min Typ Resolution Max Units 8 Integral non-linearity Bit +/-0.5 Differential non-linearity -0.3 0.3 ADC clock frequency = 6MHz LSB Offset error +/-1 Gain error +/-1 Note: 1.
ATUC64/128/256L3/4U 35.9.8 Analog Comparator Characteristics Table 35-35. Analog Comparator Characteristics Symbol Parameter Condition Positive input voltage range(3) Min Typ Max -0.2 Units VVDDIO + 0.3 V Negative input voltage range(3) Statistical offset(3) -0.2 VVDDIO - 0.6 VACREFN = 1.
ATUC64/128/256L3/4U 35.9.9.2 Strong Pull-up Pull-down Table 35-37. Strong Pull-up Pull-down Parameter Min Typ Pull-down resistor 1 Pull-up resistor 1 Max Unit kOhm 35.9.10 USB Transceiver Characteristics The USB on-chip buffers comply with the Universal Serial Bus (USB) v2.0 standard. All AC parameters related to these buffers can be found within the USB 2.0 electrical specifications. 35.9.10.1 Electrical Characteristics Table 35-38.
ATUC64/128/256L3/4U 35.10 Timing Characteristics 35.10.1 Startup, Reset, and Wake-up Timing The startup, reset, and wake-up timings are calculated using the following formula: t = t CONST + N CPU t CPU Where t CONST and N CPU are found in Table 35-39. t CPU is the period of the CPU clock. If a clock source other than RCSYS is selected as the CPU clock, the oscillator startup time, t OSCSTART , must be added to the wake-up time from the stop, deepstop, and static sleep modes.
ATUC64/128/256L3/4U 35.10.3 USART in SPI Mode Timing 35.10.3.1 Master mode Figure 35-9. USART in SPI Master Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI0 USPI1 MOSI USPI2 Figure 35-10. USART in SPI Master Mode with (CPOL= 0 and CPHA= 1) or (CPOL= 1 and CPHA= 0) SPCK MISO USPI3 USPI4 MOSI USPI5 Table 35-41.
ATUC64/128/256L3/4U Maximum SPI Frequency, Master Output The maximum SPI master output frequency is given by the following formula: 1 f CLKSPI 2 f SPCKMAX = MIN (f PINMAX,------------ -----------------------------) SPIn 9 Where SPIn is the MOSI delay, USPI2 or USPI5 depending on CPOL and NCPHA. f PINMAX is the maximum frequency of the SPI pins. Please refer to the I/O Pin Characteristics section for the maximum frequency of the pins. f CLKSPI is the maximum frequency of the CLK_SPI.
ATUC64/128/256L3/4U Figure 35-12. USART in SPI Slave Mode with (CPOL= CPHA= 0) or (CPOL= CPHA= 1) SPCK MISO USPI9 MOSI USPI10 USPI11 Figure 35-13. USART in SPI Slave Mode, NPCS Timing USPI12 USPI13 USPI14 USPI15 SPCK, CPOL=0 SPCK, CPOL=1 NSS Table 35-42.
ATUC64/128/256L3/4U Maximum SPI Frequency, Slave Input Mode The maximum SPI slave input frequency is given by the following formula: f CLKSPI 2 1 f SPCKMAX = MIN (----------------------------,------------) 9 SPIn Where SPIn is the MOSI setup and hold time, USPI7 + USPI8 or USPI10 + USPI11 depending on CPOL and NCPHA. f CLKSPI is the maximum frequency of the CLK_SPI. Refer to the SPI chapter for a description of this clock.
ATUC64/128/256L3/4U Figure 35-15. SPI Master Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI3 SPI4 MOSI SPI5 Table 35-43. SPI Timing, Master Mode(1) Symbol Parameter SPI0 MISO setup time before SPCK rises SPI1 MISO hold time after SPCK rises SPI2 SPCK rising to MOSI delay SPI3 MISO setup time before SPCK falls SPI4 MISO hold time after SPCK falls SPI5 SPCK falling to MOSI delay Note: Conditions Min Max Units 33.4 + (tCLK_SPI)/2 VVDDIO from 3.0V to 3.
ATUC64/128/256L3/4U 35.10.4.2 Slave mode Figure 35-16. SPI Slave Mode with (CPOL= 0 and NCPHA= 1) or (CPOL= 1 and NCPHA= 0) SPCK MISO SPI6 MOSI SPI7 SPI8 Figure 35-17. SPI Slave Mode with (CPOL= NCPHA= 0) or (CPOL= NCPHA= 1) SPCK MISO SPI9 MOSI SPI10 SPI11 Figure 35-18.
ATUC64/128/256L3/4U Table 35-44. SPI Timing, Slave Mode(1) Symbol Parameter SPI6 SPCK falling to MISO delay SPI7 MOSI setup time before SPCK rises SPI8 MOSI hold time after SPCK rises SPI9 SPCK rising to MISO delay SPI10 MOSI setup time before SPCK falls SPI11 MOSI hold time after SPCK falls SPI12 NPCS setup time before SPCK rises SPI13 NPCS hold time after SPCK falls 1.1 SPI14 NPCS setup time before SPCK falls 3.3 SPI15 NPCS hold time after SPCK rises 0.
ATUC64/128/256L3/4U TWIM and TWIS user interface registers. Please refer to the TWIM and TWIS sections for more information. Table 35-45. TWI-Bus Timing Requirements Minimum Symbol Parameter Mode Requirement Standard( TWCK and TWD rise time tr TWCK and TWD fall time tHD-STA (Repeated) START hold time tSU-STA (Repeated) START set-up time tSU-STO STOP set-up time tHD-DAT Data hold time tSU-DAT- Data set-up time Standard 20 + 0.1Cb 300 - 300 20 + 0.1Cb 300 0.6 Standard 4.7 Fast 0.
ATUC64/128/256L3/4U 35.10.6 JTAG Timing Figure 35-19. JTAG Interface Signals JTAG2 TCK JTAG0 JTAG1 TMS/TDI JTAG3 JTAG4 JTAG7 JTAG8 TDO JTAG5 JTAG6 Boundary Scan Inputs Boundary Scan Outputs JTAG9 JTAG10 Table 35-46. JTAG Timings(1) Symbol Parameter JTAG0 TCK Low Half-period 21.8 JTAG1 TCK High Half-period 8.6 JTAG2 TCK Period 30.
ATUC64/128/256L3/4U 36. Mechanical Characteristics 36.1 36.1.1 Thermal Considerations Thermal Data Table 36-1 summarizes the thermal resistance data depending on the package. Table 36-1. 36.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ JA Junction-to-ambient thermal resistance Still Air TQFP48 54.4 JC Junction-to-case thermal resistance TQFP48 15.7 JA Junction-to-ambient thermal resistance QFN48 26.0 JC Junction-to-case thermal resistance QFN48 1.
ATUC64/128/256L3/4U 36.2 Package Drawings Figure 36-1. TQFP-48 Package Drawing Table 36-2. Device and Package Maximum Weight 140 Table 36-3. mg Package Characteristics Moisture Sensitivity Level Table 36-4.
ATUC64/128/256L3/4U Figure 36-2. QFN-48 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 36-5. Device and Package Maximum Weight 140 Table 36-6. mg Package Characteristics Moisture Sensitivity Level Table 36-7.
ATUC64/128/256L3/4U Figure 36-3. TLLGA-48 Package Drawing Table 36-8. Device and Package Maximum Weight 39.3 Table 36-9. mg Package Characteristics Moisture Sensitivity Level MSL3 Table 36-10.
ATUC64/128/256L3/4U Figure 36-4. TQFP-64 Package Drawing Table 36-11. Device and Package Maximum Weight 300 mg Table 36-12. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-13.
ATUC64/128/256L3/4U Figure 36-5. QFN-64 Package Drawing Note: The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability. Table 36-14. Device and Package Maximum Weight 200 mg Table 36-15. Package Characteristics Moisture Sensitivity Level MSL3 Table 36-16.
ATUC64/128/256L3/4U 36.3 Soldering Profile Table 36-17 gives the recommended soldering profile from J-STD-20. Table 36-17.
ATUC64/128/256L3/4U 37. Ordering Information Table 37-1.
ATUC64/128/256L3/4U Table 37-1.
ATUC64/128/256L3/4U 38. Errata 38.1 38.1.1 Rev. C SCIF 1. The RC32K output on PA20 is not always permanently disabled The RC32K output on PA20 may sometimes re-appear. Fix/Workaround Before using RC32K for other purposes, the following procedure has to be followed in order to properly disable it: - Run the CPU on RCSYS - Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT - Enable RC32K by writing a one to SCIF.RC32KCR.
ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
ATUC64/128/256L3/4U eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency. This results in premature loss of charge from the sense capacitors and thus increased variability of the acquired count values. Fix/Workaround Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11, 13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register. 2.
ATUC64/128/256L3/4U - Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as zero. 2. PLLCOUNT value larger than zero can cause PLLEN glitch Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN signal during asynchronous wake up. Fix/Workaround The lock-masking mechanism for the PLL should not be used. The PLLCOUNT field of the PLL Control Register should always be written to zero. 3.
ATUC64/128/256L3/4U 4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK. Fix/Workaround When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1 if CSRn.CPOL=1 and CSRn.NCPHA=0. 5.
ATUC64/128/256L3/4U Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Status Register before enabling the interrupt. 38.3.6 TC 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped.
ATUC64/128/256L3/4U Issue a dummy read to address 0x100000000 before MEMORY_SPEED_REQUEST command and use this formula instead: issuing the 7f aw f sab = ---------------CV – 3 38.4 Flash 2. Corrupted data in flash may happen after flash page write operations After a flash page write operation from an external programmer, reading (data read or code fetch) in flash may fail. This may lead to an exception or to others errors derived from this corrupted read access.
ATUC64/128/256L3/4U The flash programming time is now: Table 38-1. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Conditions Min Typ Max Unit 7.5 7.5 fCLK_HSB= 50MHz 1 ms 9 fCLK_HSB= 115kHz 250 Fix/Workaround None. 4. Power Manager 5.
ATUC64/128/256L3/4U Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator may not go back to zero after the PLL oscillator has been disabled. This can cause the propagation of clock signals with the wrong frequency to parts of the system that use the PLL clock. Fix/Workaround PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL has been turned off, a delay of 30us must be observed after the PLL has been enabled again before the SCIF.
ATUC64/128/256L3/4U 38.5.5 GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 38.5.6 SPI 1.
ATUC64/128/256L3/4U 38.5.7 TWI 1. TWIS may not wake the device from sleep mode If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condition, the CPU may not wake upon a TWIS address match. The request is NACKed. Fix/Workaround When using the TWI address match to wake the device from sleep, do not switch to sleep modes deeper than Frozen.
ATUC64/128/256L3/4U Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 38.5.10 ADCIFB 1. ADCIFB DMA transfer does not work with divided PBA clock DMA requests from the ADCIFB will not be performed when the PBA clock is slower than the HSB clock.
ATUC64/128/256L3/4U 38.5.12 aWire 1. aWire MEMORY_SPEED_REQUEST command does not return correct CV The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to the formula in the aWire Debug Interface chapter. Fix/Workaround Issue a dummy read to address 0x100000000 before issuing the MEMORY_SPEED_REQUEST command and use this formula instead: 7f aw f sab = ---------------CV – 3 38.5.13 Flash 5.
ATUC64/128/256L3/4U 39. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 39.1 39.2 39.3 Rev. D – 06/2013 1. Updated the datasheet with a new ATmel blue logo and the last page. 2. Added Flash errata. Rev. C – 01/2012 1. Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz. 2. Block Diagram: GCLK_IN is input, not output.
ATUC64/128/256L3/4U Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 2.1 Block Diagram ..................................................................................................
ATUC64/128/256L3/4U 7.8 8 9 Module Configuration ......................................................................................79 USB Interface (USBC) ............................................................................ 81 8.1 Features ..........................................................................................................81 8.2 Overview ..........................................................................................................81 8.3 Block Diagram ..
ATUC64/128/256L3/4U 11.5 User Interface ................................................................................................188 11.6 Module Configuration ....................................................................................196 12 Interrupt Controller (INTC) .................................................................. 198 12.1 Features ........................................................................................................198 12.2 Overview .............
ATUC64/128/256L3/4U 15.7 Module Configuration ....................................................................................351 16 Watchdog Timer (WDT) ....................................................................... 352 16.1 Features ........................................................................................................352 16.2 Overview ........................................................................................................352 16.3 Block Diagram ........
ATUC64/128/256L3/4U 20 Universal Synchronous Asynchronous Receiver Transmitter (USART) 434 20.1 Features ........................................................................................................434 20.2 Overview ........................................................................................................434 20.3 Block Diagram ...............................................................................................435 20.4 I/O Lines Description .........................
ATUC64/128/256L3/4U 23.4 Block Diagram ...............................................................................................562 23.5 Application Block Diagram .............................................................................563 23.6 I/O Lines Description .....................................................................................563 23.7 Product Dependencies ..................................................................................563 23.
ATUC64/128/256L3/4U 27 Peripheral Event System ..................................................................... 683 27.1 Features ........................................................................................................683 27.2 Overview ........................................................................................................683 27.3 Peripheral Event System Block Diagram .......................................................683 27.4 Functional Description ..........
ATUC64/128/256L3/4U 30.9 User Interface ................................................................................................755 30.10 Module Configuration ....................................................................................769 31 Capacitive Touch Module (CAT) ......................................................... 770 31.1 Features ........................................................................................................770 31.2 Overview ...................
ATUC64/128/256L3/4U 34.6 aWire Debug Interface (AW) .........................................................................880 35 Electrical Characteristics .................................................................... 897 35.1 Absolute Maximum Ratings* .........................................................................897 35.2 Supply Characteristics ...................................................................................897 35.3 Maximum Clock Frequencies ...................
Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Roa D-85748 Garching b. Munich Tokyo 141-0032 Tel: (+1) (408) 441-0311 Kwun Tong, Kowloon GERMANY JAPAN Fax: (+1) (408) 487-2600 HONG KONG Tel: (+49) 89-31970-0 Tel: (+81) (3) 6417-0300 www.atmel.
