Datasheet

ManualsBrandsMICROCHIP TECHNOLOGY ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller TQFP 48 (7x7) 32-Bit 48 MHz I/O number 35

Features

• High Performance, Low Power 32-bit AVR

Microcontroller

– Compact Single-Cycle RISC Instruction Set Including DSP Instructions

– Read-Modify-Write Instructions and Atomic Bit Manipulation

– Performance

• Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State)

• Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State)

• Multi-Hierarchy Bus System

– High-Performance Data Transfers on Separate Buses for Increased Performance

– 7 Peripheral DMA Channels Improve Speed for Peripheral Communication

• Internal High-Speed Flash

– 128Kbytes, and 64Kbytes Versions

– Single-Cycle Access up to 24MHz

– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed

– 4ms Page Programming Time and 8ms Full-Chip Erase Time

– 100,000 Write Cycles, 15-year Data Retention Capability

– Flash Security Locks and User Defined Configuration Area

• Internal High-Speed SRAM, Single-Cycle Access at Full Speed

–16Kbytes

• Interrupt Controller (INTC)

– Autovectored Low Latency Interrupt Service with Programmable Priority

• External Interrupt Controller (EIC)

• System Functions

– Power and Clock Manager

– SleepWalking

™

Power Saving Control

– Internal System RC Oscillator (RCSYS)

– 32 KHz Oscillator

– Clock Failure Detection

– One Multipurpose Oscillator and two Phase Locked Loop (PLL)

• Windowed Watchdog Timer (WDT)

• Asynchronous Timer (AST) with Real-Time Clock Capability

– Counter or Calendar Mode Supported

• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency

• Universal Serial Bus (USB)

– Device 2.0 full speed and low speed

– Flexible End-Point Configuration and Management

– On-chip Transceivers Including Pull-Ups

• Three 16-bit Timer/Counter (TC) Channels

– External Clock Inputs, PWM, Capture and Various Counting Capabilities

• 7 PWM Channels (PWMA)

– 12-bit PWM up to 150MHz Source Clock

• Three Universal Synchronous/Asynchronous Receiver/Transmitters (USART)

– Independent Baudrate Generator, Support for SPI

– Support for Hardware Handshaking

• One Master/Slave Serial Peripheral Interfaces (SPI) with Chip Select Signals

– Up to 15 SPI Slaves can be Addressed

32133D–11/2011

32-bit AVR

Microcontroller

ATUC128D3

ATUC64D3

ATUC128D4

ATUC64D4

Summary

Summary of content (69 pages)

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Features • High Performance, Low Power 32-bit AVR® Microcontroller • • • • • • • • • • • • • • – Compact Single-Cycle RISC Instruction Set Including DSP Instructions – Read-Modify-Write Instructions and Atomic Bit Manipulation – Performance • Up to 61 DMIPS Running at 48MHz from Flash (1 Flash Wait State) • Up to 34 DMIPS Running at 24MHz from Flash (0 Flash Wait State) Multi-Hierarchy Bus System – High-Performance Data Transfers on Separate Buses for Increased Performance – 7 Peripheral DMA Channels
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UC3D • • • • • • • • • One Master and One Slave Two-Wire Interfaces (TWI), 400kbit/s I2C-compatible One 8-channel Analog-To-Digital Converter (ADC) One Inter-IC Sound Controller (IISC) with Stereo Capabilities Autonomous Capacitive Touch Button (QTouch®) Capture – Up to 25 Touch Buttons – QWheel® and QSlide® Compatible QTouch® Library Support – Capacitive Touch Buttons, Sliders, and Wheels – QTouch® and QMatrix® Acquisition – Hardware assisted QTouch® Acquisition One Programmable Glue Logic Controller(G
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UC3D 1. Description The UC3D is a complete System-On-Chip microcontroller based on the AVR32UC RISC processor running at frequencies up to 48 MHz. AVR32UC is a high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption, high code density, and high performance. The processor implements a fast and flexible interrupt controller for supporting modern operating systems and real-time operating systems.
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UC3D The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using the QTouch® technology. Capacitive touch sensors use no external mechanical components, unlike normal push buttons, and therefore demand less maintenance in the user application. The CAT module allows up to 25 touch sensors. One touch sensor can be configured to operate autonomously without software interaction,allowing wakeup from sleep modes when activated.
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UC3D 2.
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UC3D 2.2 Configuration Summary Table 2-1.
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UC3D 3. Package and Pinout 3.1 Package The device pins are multiplexed with peripheral functions as described in Section 3.2. TQFP48/QFN48 Pinout 36 35 34 33 32 31 30 29 28 27 26 25 VDDIO PA23 PA22 PA21 PA20 PA19 PA18 PA17 PA16 PA15 PA14 PA13 Figure 3-1.
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UC3D TQFP64/QFN64 Pinout 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 VDDIO PA23 PA22 PA21 PA20 PB07 PA29 PA28 PA19 PA18 PB06 PA17 PA16 PA15 PA14 PA13 Figure 3-2.
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UC3D Table 3-1.
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UC3D Table 3-1.
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UC3D 3.2.4 Oscillator Pinout The oscillators are not mapped to the normal GPIO functions and their muxings are controlled by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more information about this. Table 3-4. Oscillator Pinout 48-pin Package 64-pin Package Pin Oscillator Function 30 39 PA18 XIN0 31 40 PA19 XOUT0 22 30 PA11 XIN32 23 31 PA12 XOUT32 3.2.
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UC3D 4. Signal Descriptions The following table gives details on signal name classified by peripheral. Table 4-1.
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UC3D Table 4-1.
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UC3D Table 4-1. Signal Descriptions List EXTTRIG ADCIFD EXTTRIG AD7 - AD0 ADC Inputs Input Analog Power VDDIO Digital I/O Power Supply Power Input 3.0 V to 3.6V. VDDANA Analog Power Supply Power Input 3.0 V to 3.6V ADVREF Analog Reference Voltage Power Input 2.6 V to 3.6 V VDDCORE Core Power Supply Power Input 1.65 V to 1.95 V VDDIN Voltage Regulator Input Power Input 3.0 V to 3.6V VDDOUT Voltage Regulator Output Power Output 1.65 V to 1.
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UC3D independently for each I/O line through the GPIO Controller. After reset, I/O lines default as inputs with pull-up resistors disabled. 4.1.5 4.2 4.2.1 High drive pins Four I/O lines can be used to drive twice current than other I/O capability (see Electrical Characteristics section). 48-pin Package 64-pin Package Pin Name 32 44 PA20 33 45 PA21 34 46 PA22 35 47 PA23 Power Considerations Power Supplies The UC3D has several types of power supply pins: • VDDIO: Powers Digital I/O lines.
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UC3D Figure 4-1. Supply Decoupling 3.3V VDDIN CIN2 CIN1 1.8V 1.8V Regulator VDDOUT COUT2 COUT1 For decoupling recommendations for VDDIO, VDDANA and VDDCORE, please refer to the Schematic checklist. 4.2.3 Regulator Connection The UC3D supports two power supply configurations: • 3.3V single supply mode • 3.3V - 1.8V dual supply mode 4.2.3.1 3.3V Single Supply Mode In 3.3V single supply mode the internal regulator is connected to the 3.3V source (VDDIN pin).
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UC3D Figure 4-2. 3.3V Single Power Supply mode + 3.0-3.6V - VDDIN VDDIO GND I/O Pins VDDOUT 1.65-1.95V Linear Regulator VDDCORE ADC VDDANA 3.0-3.
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UC3D 4.2.3.2 3.3V + 1.8V Dual Supply Mode In dual supply mode the internal regulator is not used (unconnected), VDDIO is powered by 3.3V supply and VDDCORE is powered by a 1.8V supply as shown in Figure 4-3. Figure 4-3. 3.3V + 1.8V Dual Power Supply Mode. + 3.0-3.6V - VDDIN VDDIO GND I/O Pins VDDOUT Linear Regulator VDDCORE 1.65-1.95V + - VDDANA ADC 3.0-3.6V 4.2.4 CPU, Peripherals, Memories, SCIF, BOD, RCSYS, PLL + - GNDANA Power-up Sequence 4.2.4.
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UC3D See Supply Characteristics table in the Electrical Characteristics chapter for the minimum rise rate value. If the application can not ensure that the minimum rise rate condition for the VDDIN power supply is met, one of the following configuration can be used: •A logic “0” value is applied during power-up on pin RESET_N until VDDIN rises above 1.2V.
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UC3D 5. Processor and Architecture Rev: 2.1.2.0 This chapter gives an overview of the AVR32UC CPU. AVR32UC is an implementation of the AVR32 architecture. A summary of the programming model, and instruction set is presented. For further details, see the AVR32 Architecture Manual and the AVR32UC Technical Reference Manual. 5.
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UC3D The register file is organized as sixteen 32-bit registers and includes the Program Counter, the Link Register, and the Stack Pointer. In addition, register R12 is designed to hold return values from function calls and is used implicitly by some instructions. 5.3 The AVR32UC CPU The AVR32UC CPU targets low- and medium-performance applications, and provides an advanced On-Chip Debug (OCD) system, and no caches. Java acceleration hardware is not implemented.
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UC3D OCD interface Reset interface Overview of the AVR32UC CPU Interrupt controller interface Figure 5-1. OCD system P ow er/ R eset control A V R 32U C C P U pipeline 5.3.
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UC3D Figure 5-2. The AVR32UC Pipeline Multiply unit MUL IF ID Prefetch unit Decode unit Regfile Read ALU LS 5.3.2 Regfile write ALU unit Load-store unit AVR32A Microarchitecture Compliance AVR32UC implements an AVR32A microarchitecture. The AVR32A microarchitecture is targeted at cost-sensitive, lower-end applications like smaller microcontrollers. This microarchitecture does not provide dedicated hardware registers for shadowing of register file registers in interrupt contexts.
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UC3D The following table shows the instructions with support for unaligned addresses. All other instructions require aligned addresses. Table 5-1. 5.3.2.4 Instructions with Unaligned Reference Support Instruction Supported Alignment ld.d Word st.
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UC3D 5.4 5.4.1 Programming Model Register File Configuration The AVR32UC register file is shown below. Figure 5-3.
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UC3D Figure 5-5. The Status Register Low Halfword Bit 15 Bit 0 - T - - - - - - - - L Q V N Z C Bit name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value Carry Zero Sign Overflow Saturation Lock Reserved Scratch Reserved 5.4.3 Processor States 5.4.3.1 Normal RISC State The AVR32 processor supports several different execution contexts as shown in Table 5-2. Table 5-2. Overview of Execution Modes, their Priorities and Privilege Levels.
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UC3D Debug state can be entered as described in the AVR32UC Technical Reference Manual. Debug state is exited by the retd instruction. 5.4.4 System Registers The system registers are placed outside of the virtual memory space, and are only accessible using the privileged mfsr and mtsr instructions. The table below lists the system registers specified in the AVR32 architecture, some of which are unused in AVR32UC.
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UC3D Table 5-3. 5.
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UC3D the entire event routine to be placed directly at the address specified by the EVBA-relative offset generated by hardware. All interrupt sources have autovectored interrupt service routine (ISR) addresses. This allows the interrupt controller to directly specify the ISR address as an address relative to EVBA. The autovector offset has 14 address bits, giving an offset of maximum 16384 bytes.
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UC3D contains information allowing the core to resume operation in the previous execution mode. This concludes the event handling. 5.5.3 Supervisor Calls The AVR32 instruction set provides a supervisor mode call instruction. The scall instruction is designed so that privileged routines can be called from any context. This facilitates sharing of code between different execution modes.
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UC3D The addresses and priority of simultaneous events are shown in Table 5-4 on page 32. Some of the exceptions are unused in AVR32UC since it has no MMU, coprocessor interface, or floatingpoint unit.
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UC3D Table 5-4.
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UC3D 6. Memories 6.
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UC3D Table 6-2.
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UC3D Table 6-2. Peripheral Address Mapping 0xFFFF6400 GLOC 0xFFFF6800 6.4 AW Glue Logic Controller - GLOC aWire - AW CPU Local Bus Mapping Some of the registers in the GPIO module are mapped onto the CPU local bus, in addition to being mapped on the Peripheral Bus. These registers can therefore be reached both by accesses on the Peripheral Bus, and by accesses on the local bus.
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UC3D 7. Boot Sequence This chapter summarizes the boot sequence of the UC3D. The behavior after power-up is controlled by the Power Manager. For specific details, refer to the Power Manager chapter. 7.1 Starting of Clocks After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a short time to allow the power to stabilize throughout the device. After reset, the device will use the System RC Oscillator (RCSYS) as clock source.
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UC3D 8. Electrical Characteristics 8.1 Disclaimer All values in this chapter are preliminary and subject to change without further notice. 8.2 Absolute Maximum Ratings* Table 8-1. Absolute Maximum Ratings Operating temperature .................................... -40°C to +85°C *NOTICE: Storage temperature ...................................... -60°C to +150°C Voltage on input pins (except for 5V pins) with respect to ground .................................................................-0.
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UC3D • Temperature = -40°C to 85°C Table 8-3. 8.
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UC3D Table 8-4. Mode Active Idle Frozen Standby Stop Deepstop Static Power Consumption for Different Operating Modes Conditions Consumption Typ Unit 0.3105xf(MHz) + 0.2707 mA/MHz Same conditions at 48MHz 15.17 mA See Active mode conditions 0.1165xf(MHz) + 0.1457 mA/MHz Same conditions at 48MHz 5.74 mA See Active mode conditions 0.0718xf(MHz) + 0.0903 mA/MHz Same conditions at 48MHz 3.54 mA See Active mode conditions 0.0409xf(MHz) + 0.0935 mA/MHz Same conditions at 48MHz 2.
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UC3D Figure 8-1. Measurement Schematic, External Core Supply VDDANA VDDIO Amp0 VDDIN Internal Voltage Regulator VDDOUT Amp1 8.5.1 VDDCORE Peripheral Power Consumption The values in Table 8-5 are measured values of power consumption under the following conditions. • Operating conditions external core supply (Figure 8-1) – VVDDIN = 3.3V – VVDDCORE = 1.8V, supplied by the internal regulator – Corresponds to the 3.3V + 1.
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UC3D • I/Os are inactive with internal pull-up Consumption idle is the added current consumption when turning the module clock on and the module is uninitialized. Consumption active is the added current consumption when the module clock is turned on and when the module is doing a typical set of operations. Table 8-5. Typical Current Consumption by Peripheral Peripheral ADCIFD Unit 3.6 AST 4.5 AW USART 9.8 CAT 14 EIC 2.3 FREQM 1.1 GLOC 1.3 GPIO 10.6 IISC 4.7 PWMA 5.6 SPI 6.3 TC 7.
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UC3D Table 8-6. Symbol IOL Normal I/O Pin Characteristics(1) Parameter Output low-level current IOH Output high-level current Condition Min VVDD = 3.0V VVDD = 3.0V VVDD = 3.0V, load = 10 pF Output frequency(2) FMAX VVDD = 3.0V, load = 30 pF VVDD = 3.0V, load = 10 pF Rise time(2) tRISE VVDD = 3.0V, load = 30 pF VVDD = 3.0V, load = 10 pF Fall time(2) tFALL VVDD = 3.
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UC3D Table 8-7. High-drive I/O Pin Characteristics(1) Symbol Parameter Condition VOH Output high-level voltage VVDD = 3.0V, IOH = 6mA IOL Output low-level current VVDD = 3.0V 16 mA IOH Output high-level current VVDD = 3.0V 16 mA FMAX Output frequency VVDD = 3.0V, load = 10 pF 471 MHz VVDD = 3.0V, load = 30 pF 249 MHz tRISE Rise time, all High-drive I/O pins VVDD = 3.0V, load = 10 pF 0.86 ns VVDD = 3.0V, load = 30 pF 1.70 ns tFALL Fall time VVDD = 3.0V, load = 10 pF 1.
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UC3D 8.7 Oscillator Characteristics 8.7.1 Oscillator 0 (OSC0) Characteristics 8.7.1.1 Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN. Table 8-10. Digital Clock Characteristics Symbol Parameter fCPXIN XIN clock frequency tCPXIN XIN clock duty cycle 8.7.1.
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UC3D Figure 8-2. Oscillator Connection C LE X T XO U T U C 3D Ci CL XIN C LEX T 8.7.2 32KHz Crystal Oscillator (OSC32K) Characteristics 8.7.2.1 Table 8-12. Digital Clock Characteristics The following table describes the characteristics for the oscillator when a digital clock is applied on XIN32. Digital Clock Characteristics Symbol Parameter fCPXIN XIN32 clock frequency tCPXIN XIN32 clock duty cycle Conditions Min Typ Max 32.
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UC3D 8.7.3 Phase Locked Loop (PLL) Characteristics Table 8-14. Phase Lock Loop Characteristics Symbol Parameter FOUT VCO Output Frequency FIN Input Frequency IPLL Current Consumption tSTARTUP Startup time, from enabling the PLL until the PLL is locked 8.7.4 Conditions Symbol Max.
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UC3D Table 8-18. Flash Characteristics Symbol Parameter TFPP Page programming time TFPE Page erase time TFFP Fuse programming time TFEA Full chip erase time (EA) TFCE JTAG chip erase time (CHIP_ERASE) Table 8-19.
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UC3D Table 8-21. Decoupling Requirements Symbol Parameter CIN2 Typ Techno. Units Input regulator capacitor 2 4.7 X7R nF COUT1 Output regulator capacitor 1 470 NPO nF COUT2 Output regulator capacitor 2 2.2 X7R µF 8.9.2 Condition ADC Characteristics Table 8-22. Channel Conversion Time and ADC Clock Parameter Conditions Min. Typ. Max.
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UC3D Table 8-25. Transfer Characteristics in 8-bit mode Parameter Conditions Differential Non-linearity Min. Typ. Max. Unit ADC Clock = 5 MHz 0.3 0.5 LSB ADC Clock = 8 MHz 0.5 1.0 LSB Offset Error ADC Clock = 5 MHz -0.5 0.5 LSB Gain Error ADC Clock = 5 MHz -0.5 0.5 LSB Max. Unit 3 LSB Table 8-26. Transfer Characteristics in 10-bit mode Parameter Conditions Min. Typ. Resolution 10 Bit Absolute Accuracy ADC Clock = 5 MHz Integral Non-linearity ADC Clock = 5 MHz 1.
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UC3D 8.9.4 Reset Sequence Table 8-29. Electrical Characteristics Symbol Parameter Conditions VDDRR VDDCORE rise rate to ensure poweron-reset 2.5 VDDFR VDDCORE fall rate to ensure poweron-reset 0.01 VPOR+ Rising threshold voltage: voltage up to which device is kept under reset by POR on rising VDDCORE Rising VDDCORE: VRESTART -> VPOR+ 1.4 VPOR- Falling threshold voltage: voltage when POR resets device on falling VDDCORE Falling VDDCORE: 1.8V -> VPOR+ 1.
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UC3D Figure 8-4. VDDCORE MCU Cold Start-Up RESET_N Externally Driven VPOR- VPOR+ VRESTART RESET_N Internal POR Reset TPOR TRST TSSU1 Internal MCU Reset Figure 8-5. MCU Hot Start-Up VDDCORE RESET_N BOD Reset WDT Reset TSSU2 Internal MCU Reset In dual supply configuration, the power up sequence must be carefully managed to ensure a safe startup of the device in all conditions.
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UC3D Figure 8-6. Dual Supply Configuration V D D IO m in 2. 5 V V DD /m R sm R ini m um V D D IO V p or+ m in VDDCORE < 50 0 u s TSSU1 TRST Interna l POR (a ctive lo w ) F irst ins tructio n fe tch ed in fla sh 8.9.5 RESET_N Characteristics Table 8-30. RESET_N Waveform Parameters Symbol Parameter tRESET RESET_N minimum pulse width 8.10 Conditions Min. Typ. Max. 10 Unit ns USB Transceiver Characteristics 8.10.
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UC3D 9. Mechanical Characteristics 9.1 9.1.1 Thermal Considerations Thermal Data Table 9-1 summarizes the thermal resistance data depending on the package. Table 9-1. 9.1.2 Thermal Resistance Data Symbol Parameter Condition Package Typ θJA Junction-to-ambient thermal resistance Still Air TQFP48 65.1 θJC Junction-to-case thermal resistance TQFP48 23.4 θJA Junction-to-ambient thermal resistance QFN48 29.2 θJC Junction-to-case thermal resistance QFN48 2.
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UC3D 9.2 Package Drawings Figure 9-1. TQFP-64 package drawing Table 9-2. Device and Package Maximum Weight Weight Table 9-3. 300 mg Package Characteristics Moisture Sensitivity Level Table 9-4.
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UC3D Figure 9-2. TQFP-48 package drawing Table 9-5. Device and Package Maximum Weight Weight Table 9-6. 100 mg Package Characteristics Moisture Sensitivity Level Table 9-7.
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UC3D Figure 9-3. QFN-48 Package Drawing Table 9-8. Device and Package Maximum Weight Weight Table 9-9. 100 mg Package Characteristics Moisture Sensitivity Level Table 9-10.
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UC3D Figure 9-4. QFN-64 package drawing Table 9-11. Device and Package Maximum Weight Weight Table 9-12. 200 mg Package Characteristics Moisture Sensitivity Level Table 9-13.
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UC3D 9.3 Soldering Profile Table 9-14 gives the recommended soldering profile from J-STD-20. Table 9-14.
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UC3D 10. Ordering Information Table 10-1.
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UC3D 11. Errata 11.1 Rev. C 11.1.1 SPI 1. SPI disable does not work in SLAVE mode SPI disable does not work in SLAVE mode. Fix/Workaround Read the last received data, then perform a software reset by writing a one to the Software Reset bit in the Control Register (CR.SWRST). 2. PCS field in receive data register is inaccurate The PCS field in the SPI_RDR register does not accurately indicate from which slave the received data is read. Fix/Workaround None. 3. SPI data transfer hangs with CSR0.
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UC3D 11.1.2 TWIS 1. Clearing the NAK bit before the BTF bit is set locks up the TWI bus When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Register (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to attempt to continue transmitting data, thus locking up the bus. Fix/Workaround Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been set. 11.1.3 PWMA 1. The SR.READY bit cannot be cleared by writing to SCR.
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UC3D 4. Disabling SPI has no effect on the SR.TDRE bit Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer is empty, and this data will be lost. Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 5.
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UC3D 11.3 11.3.1 Rev. A GPIO 1. Clearing Interrupt flags can mask other interrupts When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening in the same clock cycle will not be registered. Fix/Workaround Read the PVR register of the port before and after clearing the interrupt to see if any pin change has happened while clearing the interrupt. If any change occurred in the PVR between the reads, they must be treated as an interrupt. 11.3.2 Power Manager 1.
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UC3D Fix/Workaround Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the SPI and PDCA. 8. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and NCPHA=0 When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one (CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0, then an additional pulse will be generated on SCK.
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UC3D 11.3.3 Timer Counter 1. Channel chaining skips first pulse for upper channel When chaining two channels using the Block Mode Register, the first pulse of the clock between the channels is skipped. Fix/Workaround Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle for the upper channel. After the dummy cycle has been generated, indicated by the SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real values. 11.3.4 TWIS 1.
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UC3D 12. Datasheet Revision History Please note that the referring page numbers in this section are referred to this document. The referring revision in this section are referring to the document revision. 12.1 Rev. A – 11/2009 1. 12.2 Rev. B – 04/2011 1. 12.3 Minor. Rev. C – 07/2011 1. 12.4 Initial revision. Final revision. Rev. D – 11/2011 1. 2. Adding errata for silicon Revision C .
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UC3D Table of Contents Features ..................................................................................................... 1 1 Description ............................................................................................... 3 2 Overview ................................................................................................... 5 3 4 5 6 7 8 2.1 Block Diagram ...................................................................................................5 2.
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UC3D 9 8.7 Oscillator Characteristics .................................................................................44 8.8 Flash Characteristics .......................................................................................46 8.9 Analog Characteristics .....................................................................................47 8.10 USB Transceiver Characteristics .....................................................................52 Mechanical Characteristics .............
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Headquarters International Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600 Atmel Asia Unit 1-5 & 16, 19/F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon Hong Kong Tel: (852) 2245-6100 Fax: (852) 2722-1369 Atmel Europe Le Krebs 8, Rue Jean-Pierre Timbaud BP 309 78054 Saint-Quentin-enYvelines Cedex France Tel: (33) 1-30-60-70-00 Fax: (33) 1-30-60-71-11 Atmel Japan 9F, Tonetsu Shinkawa Bldg.