Datasheet

93
32133D–11/2011
UC3D
10.7 Module Configuration
The specific configuration for each PDCA instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
The table below defines the valid Peripheral Identifiers (PIDs). The direction is specified as
observed from the memory, so RX means transfers from peripheral to memory and TX means
from memory to peripheral.
Table 10-5. PDCA Configuration
Feature PDCA
Number of channels 7
Table 10-6. Module Clock Name
Module name PB Clock Name HSB Clock Name
PDCA CLK_PDCA_PB CLK_PDCA_HSB
Table 10-7. Register Reset Values
Register Reset Value
PSR CH n n
VERSION 123
Table 10-8. Peripheral Identity Values
PID Direction Peripheral Instance Peripheral Register
0 RX USART0 RHR
1 RX USART1 RHR
2 RX USART2 RHR
3 RX SPI RDR
4 RX TWIM RHR
5 RX TWIS RHR
6 RX IISC RHR
7 RX IISC RHR
8 RX ADCIFD LCV
9 RX CAT ACOUNT
10 RX CAT DMATSR
11 RX AW RHR
12 TX USART0 THR
13 TX USART1 THR
14 TX USART2 THR
15 TX SPI TDR
16 TX TWIM THR