Datasheet

32133D–11/2011

UC3D

10.6.11 Status Register

Name: SR

Access Type: Read-only

Offset: 0x01C + n*0x040

Reset Value: 0x00000000

• TEN: Transfer Enabled

This bit is cleared when the TDIS bit in CR is written to one.

This bit is set when the TEN bit in CR is written to one.

0: Transfer is disabled for the DMA channel.

1: Transfer is enabled for the DMA channel.

31 30 29 28 27 26 25 24

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23 22 21 20 19 18 17 16

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15 14 13 12 11 10 9 8

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76543210

-------TEN