Datasheet

8
32133D–11/2011
UC3D
Figure 3-2. TQFP64/QFN64 Pinout
Note: On QFN packages, the exposed pad is not connected to anything internally, but should be sol-
dered to ground to increase board level reliability.
3.2 Peripheral Multiplexing on I/O lines
3.2.1 Multiplexed signals
Each GPIO line can be assigned to one of the peripheral functions.The following table describes
the peripheral signals multiplexed to the GPIO lines.
GND1 PB122 PA003 PA014 PA025 PB006 PB017 PB138 PA039 PA0410 PA0511 PA0612 PA0713 PA0814 PA3015 PA3116
GNDANA17
ADVREF18
VDDANA19
VDDOUT20
VDDIN21
VDDCORE22
GND23
PB0224
PB0325
PB0426
PB0527
PA0928
PA1029
PA1130
PA1231
VDDIO32
VDDIO48 PA2347 PA2246 PA2145 PA2044 PB0743 PA2942 PA2841 PA1940 PA1839 PB0638 PA1737 PA1636 PA1535 PA1434 PA1333
GND 49
PB14 - DP 50
PB15 - DM 51
PB16-VBUS 52
PB17 53
PB08 54
PB09 55
PB18 56
PB10 57
PB11 58
PA24 59
PA25 60
PA26 61
PA27 62
RESET_N 63
VDDIO 64
Table 3-1. Multiplexed Signals on I/O Pins
48-pin
Package
64-pin
Package PIN GPIO Supply Pad Type
GPIO Function
Other FunctionsABCD
3 3 PA00 0 VDDIO Normal I/O SPI - MISO PWMA - PWMA[1] GLOC - IN[0] CAT - CSB[0] JTAG-TDI
4 4 PA01 1 VDDIO Normal I/O SPI - MOSI PWMA - PWMA[2] GLOC - IN[1] CAT - CSA[1] JTAG-TDO
5 5 PA02 2 VDDIO Normal I/O SPI - SCK PWMA - PWMA[3] GLOC - IN[2] CAT - CSB[1] JTAG-TMS
7 9 PA03 3 VDDANA Analog I/O PKGANA - ADCIN0 SCIF - GCLK[0] GLOC - IN[5] CAT - CSB[2]
8 10 PA04 4 VDDANA Analog I/O PKGANA - ADCIN1 SCIF - GCLK[1] GLOC - IN[6] CAT - CSA[3]