Datasheet

743
32133D–11/2011
UC3D
Fix/Workaround
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the
SPI and PDCA.
8. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and
NCPHA=0
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,
then an additional pulse will be generated on SCK.
Fix/Workaround
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1
if CSRn.CPOL=1 and CSRn.NCPHA=0.
9. I/O Pins
10. Current leakage through pads PA09, PA10 and PB16
Pads PA09 (TWI), PA10 (TWI) and PB16 (USB VBUS) are not fully 5V tolerant. A leakage
current can be observed when a 5V voltage is applied onto those pads inputs. Their behav-
ior is normal at 3.3V
Fix/Workaround
None for pads PA09 and PA10. A voltage divider can be used for PB16 (VBUS) to bring the
input voltage down into the 3.3V range.
11. Current leakage through pads PB13, PB17 and PB18
For applications in which UC3D is considered as a drop in replacement solution to UC3B,
pads PB13, PB17 and PB18 can no longer be used as VDDCORE supply pins.Maintaining a
1.8V voltage on those inputs will however lead to a current over consumption through the
pins.
Fix/Workaround
Do not connect PB13, PB17 and PB18 when using UC3D as a drop in replacement for a
UC3B specific application.
12. IO drive strength mismatch with UC3B specification for pads PA11, PA12, PA18 and
PA19
For applications in which UC3D is considered as a drop in replacement solution to UC3B,
GPIOs PA11, PA12, PA18 and PA19 are not completely compatible in terms of drive
strength. Those pads have a 8 mA current capability on UC3B, while this is limited to 4 mA
in UC3D.
Fix/Workaround
None.
13. WDT
14. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will
issue a Watchdog reset
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-
ately issue a Watchdog reset.
Fix/Workaround
Use twice as long timeout period as needed and clear the WDT counter within the first half
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time
before the reset will be twice as long as needed.