Datasheet

730
32133D–11/2011
UC3D
Figure 32-4. MCU Cold Start-Up RESET_N Externally Driven
Figure 32-5. MCU Hot Start-Up
In dual supply configuration, the power up sequence must be carefully managed to ensure a
safe startup of the device in all conditions.
The power up sequence must ensure that the internal logic is safely powered when the internal
reset (Power On Reset) is released and that the internal Flash logic is safely powered when the
CPU fetch the first instructions.
Therefore VDDCORE rise rate (VDDRR) must be equal or superior to 2.5V/ms and VDDIO must
reach VDDIO mini value before 500 us (< TRST + TSSU1) after VDDCORE has reached V
POR+
min value.
V
POR+
VDDCORE
Internal
MCU Reset
T
SSU1
Internal
POR Reset
V
POR-
T
POR
T
RST
RESET_N
V
RESTART
VDDCORE
Internal
MCU Reset
T
SSU2
RESET_N
BOD Reset
WDT Reset