Datasheet

729
32133D–11/2011
UC3D
32.9.4 Reset Sequence
Figure 32-3.
MCU Cold Start-Up RESET_N tied to VDDIN
Table 32-29. Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
V
DDRR
VDDCORE rise rate to ensure power-
on-reset
2.5 V/ms
V
DDFR
VDDCORE fall rate to ensure power-
on-reset
0.01 400 V/ms
V
POR+
Rising threshold voltage: voltage up
to which device is kept under reset by
POR on rising VDDCORE
Rising VDDCORE:
V
RESTART
-> V
POR+
1.4 1.55 1.65 V
V
POR-
Falling threshold voltage: voltage
when POR resets device on falling
VDDCORE
Falling VDDCORE:
1.8V -> V
POR+
1.2 1.3 1.4 V
V
RESTART
On falling VDDCORE, voltage must
go down to this value before supply
can rise again to ensure reset signal
is released at V
POR+
Falling VDDCORE:
1.8V -> V
RESTART
-0.1 0.5 V
T
POR
Minimum time with VDDCORE <
V
POR-
Falling VDDCORE:
1.8V -> 1.1V
15 µs
T
RST
Time for reset signal to be propagated
to system
200 400 µs
T
SSU1
Time for Cold System Startup: Time
for CPU to fetch its first instruction
(RCosc not calibrated)
480 960 µs
T
SSU2
Time for Hot System Startup: Time for
CPU to fetch its first instruction
(RCosc calibrated)
420 µs
V
POR+
VDDCORE
Internal
MCU Reset
T
SSU1
Internal
POR Reset
V
POR-
T
POR
T
RST
RESET_N
V
RESTART