Datasheet

72
32133D–11/2011
UC3D
9.6 Module Configuration
9.6.1 Bus Matrix Connections
The bus matrix has several masters and slaves. Each master has its own bus and its own
decoder, thus allowing a different memory mapping per master. The master number in the table
below can be used to index the HMATRIX control registers. For example, HMATRIX MCFG0
register is associated with the CPU Data master interface.
Each slave has its own arbiter, thus allowing a different arbitration per slave. The slave number
in the table below can be used to index the HMATRIX control registers. For example, SCFG1 is
associated with the Internal SRAM Slave Interface.
Accesses to unused areas returns an error result to the master requesting such an access.
Table 9-3. High Speed Bus Masters
Master 0 CPU Data
Master 1 CPU Instruction
Master 2 CPU SAB
Master 3 PDCA
Master 4 USBC Built-in DMA
Table 9-4. High Speed Bus Slaves
Slave 0 Internal Flash
Slave 1 Internal SRAM
Slave 2 HSB-PB Bridge A
Slave 3 HSB-PB Bridge B