Datasheet

715
32133D–11/2011
UC3D
internal logic. Typically, output value, output enable, and input data are all available in the
boundary scan chain.
The boundary scan chain is described in the BDSL (Boundary Scan Description Language) file
available at the Atmel web site.
31.7 NanoTrace and Auxilliary Port
NanoTrace and Auxilliary(AUX) Port features have not been implemented in this chip. All refer-
ences to these concepts are invalid.
31.8 Module Configuration
The bit mapping of the Peripheral Debug Register (PDBG) is described in the following table.
Please refer to the On-Chip-Debug chapter in the AVR32UC Technical Reference Manual for
details.
Table 31-59. Bit Mapping of the Peripheral Debug Register (PDBG)
bit Peripheral
0WDT
1 AST
2ADC