Datasheet

692
32133D–11/2011
UC3D
31.5.3 Block Diagram
Figure 31-9.
JTAG and Boundary-scan Access
31.5.4 I/O Lines Description
31.5.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
Table 31-37. I/O Line Description
Pin Name Pin Description Type Active Level
RESET_N External reset pin. Used when enabling and disabling the JTAG. Input Low
TCK Test Clock Input. Fully asynchronous to system clock frequency. Input
TMS Test Mode Select, sampled on rising TCK. Input
TDI Test Data In, sampled on rising TCK. Input
TDO Test Data Out, driven on falling TCK. Output
32-bit AVR device
JTAG data registers
TAP
Controller
Instruction Register
Device Identification
Register
By-pass Register
Reset Register
Service Access Bus
interface
Boundary Scan Chain
Pins and analog blocks
Data register
scan enable
JTAG Pins
Boundary scan enable
2nd JTAG
device
JTAG master
TDITDO
Part specific registers
...
TDO TDITMS
TMS
TCK
TCK
Instruction register
scan enable
SAB
Internal I/O
lines
JTAG
TMS
TDI
TDO
TCK