Datasheet

691
32133D–11/2011
UC3D
31.5 JTAG and Boundary-scan (JTAG)
Rev: 2.2.2.4
31.5.1 Features
• IEEE1149.1 compliant JTAG Interface
• Boundary-scan Chain for board-level testing
• Direct memory access and programming capabilities through JTAG Interface
31.5.2 Overview
The JTAG Interface offers a four pin programming and debug solution, including boundary-scan
support for board-level testing.
Figure 31-9 on page 692 shows how the JTAG is connected in an 32-bit AVR device. The TAP
Controller is a state machine controlled by the TCK and TMS signals. The TAP Controller
selects either the JTAG Instruction Register or one of several Data Registers as the scan chain
(shift register) between the TDI-input and TDO-output.
The Instruction Register holds JTAG instructions controlling the behavior of a Data Register. The
Device Identification Register, Bypass Register, and the boundary-scan chain are the Data Reg-
isters used for board-level testing. The Reset Register can be used to keep the device reset
during test or programming.
The Service Access Bus (SAB) interface contains address and data registers for the Service
Access Bus, which gives access to On-Chip Debug, programming, and other functions in the
device. The SAB offers several modes of access to the address and data registers, as described
in Section 31.5.11.
Section 31.6 lists the supported JTAG instructions, with references to the description in this
document.