Datasheet

690
32133D–11/2011
UC3D
31.4.8.7 STATUS_INFO
A status message from AW.
31.4.8.8 MEMORY_SPEED
Counts the number of RC120M clock cycles it takes to sync one message to the SAB interface
and back again. The SAB clock speed ( ) can be calculated using the following formula:
31.4.9 Security Restrictions
When the security fuse in the Flash is programmed, the following aWire commands are limited:
• MEMORY_WRITE
• MEMORY_READ
Unlimited access to these instructions is restored when the security fuse is erased by the
CHIP_ERASE aWire command.
Note that the security bit will read as programmed and block these instructions also if the Flash
Controller is statically reset.
Table 31-34. STATUS_INFO Contents
Bit number Name Description
15-9 Reserved
8Protected
The protection bit in the internal flash is set. SAB access is restricted. This bit
will read as one during reset.
7 SAB busy
The SAB bus is busy with a previous transfer. This could indicate that the
CPU is running on a very slow clock, the CPU clock has stopped for some
reason or that the part is in constant reset.
6 Chip erase ongoing The Chip erase operation has not finished.
5 CPU halted This bit will be set if the CPU is halted. This bit will read as zero during reset.
4-1 Reserved
0 Reset status This bit will be set if AW has reset the CPU using the RESET command.
Table 31-35. STATUS_INFO Details
Response Details
Response value 0xC4
Additional data 2 status bytes
Table 31-36. MEMORY_SPEED Details
Response Details
Response value 0xC5
Additional data Clock cycle count (MS)
f
sab
f
sab
3f
aw
CV 3–
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