Datasheet

686
32133D–11/2011
UC3D
11. 0x04
12. 0xXX (CRC MSB)
13. 0xXX (CRC LSB)
The length field is set to 0x0007 because there are 7 bytes of additional data: 5 bytes of address
and size and 2 bytes with the number of bytes to read. The address and size field indicates one
word (four bytes) should be read from address 0x500000004.
31.4.7.11 HALT
This command tells the CPU to halt code execution for safe programming. If the CPU is not
halted during programming it can start executing partially loaded programs. To halt the proces-
sor, the aWire master should send 0x01 in the data field of the command. After programming the
halting can be released by sending 0x00 in the data field of the command.
31.4.7.12 RESET
This command resets different domains in the part. The aWire master sends a byte with the
reset value. Each bit in the reset value byte corresponds to a reset domain in the chip. If a bit is
set the reset is activated and if a bit is not set the reset is released. The number of reset domains
and their destinations are identical to the resets described in the JTAG data registers chapter
under reset register.
Table 31-21. MEMORY_READ Details
Command Details
Command value 0x81
Additional data Size, Address and Length
Possible responses
0xC1: MEMDATA (Section 31.4.8.4)
0xC2: MEMORY_READWRITE_STATUS (Section 31.4.8.5)
0x41: NACK (Section 31.4.8.2)
Table 31-22. HALT Details
Command Details
Command value 0x82
Additional data
0x01 to halt the CPU 0x00 to release the halt and reset the
device.
Possible responses
0x40: ACK (Section 31.4.8.1)
0x41: NACK (Section 31.4.8.2)
Table 31-23. RESET Details
Command Details
Command value 0x83
Additional data
Reset value for each reset domain. The number of reset
domains is part specific.
Possible responses
0x40: ACK (Section 31.4.8.1)
0x41: NACK (Section 31.4.8.2)