Datasheet

667
32133D–11/2011
UC3D
31.3 On-Chip Debug
Rev: 2.1.2.0
31.3.1 Features
• Debug interface in compliance with IEEE-ISTO 5001-2003 (Nexus 2.0) Class 2+
• JTAG or aWire access to all on-chip debug functions
• Advanced Program, Data, Ownership, and Watchpoint trace supported
• NanoTrace aWire- or JTAG-based trace access
• Auxiliary port for high-speed trace information
• Hardware support for 6 Program and 2 Data breakpoints
• Unlimited number of software breakpoints supported
• Automatic CRC check of memory regions
31.3.2 Overview
Debugging on the UC3D is facilitated by a powerful On-Chip Debug (OCD) system. The user
accesses this through an external debug tool which connects to the JTAG or aWire port and the
Auxiliary (AUX) port if implemented. The AUX port is primarily used for trace functions, and an
aWire- or JTAG-based debugger is sufficient for basic debugging.
The debug system is based on the Nexus 2.0 standard, class 2+, which includes:
• Basic run-time control
• Program breakpoints
• Data breakpoints
• Program trace
• Ownership trace
• Data trace
In addition to the mandatory Nexus debug features, the UC3D implements several useful OCD
features, such as:
• Debug Communication Channel between CPU and debugger
• Run-time PC monitoring
• CRC checking
• NanoTrace
• Software Quality Assurance (SQA) support
The OCD features are controlled by OCD registers, which can be accessed by the debugger, for
instance when the NEXUS_ACCESS JTAG instruction is loaded. The CPU can also access
OCD registers directly using mtdr/mfdr instructions in any privileged mode. The OCD registers
are implemented based on the recommendations in the Nexus 2.0 standard, and are detailed in
the AVR32UC Technical Reference Manual.
31.3.3 I/O Lines Description
The OCD AUX trace port contains a number of pins, as shown in Table 31-5 on page 668.
These are multiplexed with I/O Controller lines, and must explicitly be enabled by writing OCD
registers before the debug session starts. The AUX port is mapped to two different locations,