Datasheet

636
32133D–11/2011
UC3D
28.8Module configuration
The specific configuration for each ADC instance is listed in the following tables.The module bus
clocks listed here are connected to the system bus clocks according to the table in the System
Bus Clock Connections section.
Table 28-5. Module configuration
Feature Connected to
Internal Trigger TC0, output A0
Table 28-6. ADCIFD Clocks
Clock Name Description
CLK_ADCIFD Clock for the ADCIFD bus interface
GCLK_ADCIFD
Conversion clock.
The generic clock used for the ADCIFD is GCLK8
Table 28-7. Register Reset Values
Register Reset Value
VERSION 0x0000 0100
PARAMETER 0x0000 0808