Datasheet

612
32133D–11/2011
UC3D
28.6.12 Conversion results
If the Half Word Left Adjust (HWLA) bit in the SEQCFG register is set, then the result will be left
adjusted on the 16 lower bits of the LCV register. Otherwise, results will be right-adjusted.All
conversion results are signed in two's complement representation. Extra bits depending on reso-
lution and left adjust settings are padded with zeroes.
28.6.13 Sequencer trigger event (STRIG)
The sources must be configured through the TRGSEL field of the SEQCFG register
(SEQCFG.TRGSEL). Selecting the event controller source allows any event controller source to
generate a sequencer trigger event (STRIG). By configuring the continuous mode, STRIG will
be generated continuously.
The ADC can serve a maximum of one STRIG every 10 GCLK periods. Extra STRIG will be
ignored. User will be informed thanks to the Sequencer Missed Trigger Event (SMTRG) field of
the SR register (SR.SMTRG). If the STRIG frequency provided by the event controller exceeds
the ADC capability, the event controller will generate an underrun status.
28.6.14 Internal Timer
The ADCIFD embeds an internal timer used as a trigger source which can be configured by set-
ting the ITMC field of the ITIMER register (ITIMER.ITMC).
Internal Timer Trigger Period=
(ITMC+1)*T(GCLK)
Once set as a STRIG source, the internal timer has to be started by writing a '1' in the TSTART
bit of the CR register (CR.TSTART). It can be stopped in the same way by writing a '1' in the
TSTOP bit of the CR register (CR.TSTOP). The current status of the internal timer can be read
from the Timer Busy field of the SR register (SR.TBUSY): 0 means stopped, 1 means running. In
addition when the internal timer is running, if ITIMER.ITMC is written to change the internal timer
timeout frequency, the internal counter is cleared to avoid rollover phenomena.
Note: It is possible to generate an internal timer event each GCLK period by writing 0x0 in
ITIMER.ITMC and by selecting the internal timer as a STRIG source
28.6.15 Peripheral DMA Controller (PDC) capability
There is one PDC channel. The LCV register contains the last converted value of the sequencer
according to the conversion result format. The LCV register is updated each time the sequencer
ends a conversion. If the last converted value has not been read, there’s an overrun, the LOVR
bit in the SR register indicates that at least one overrun error occurred. The LOVR bit of the SR
register is cleared by writing a ‘1’ in the LOVR fields of the SCR register.
Note: PDC transfers are 16 bits wide.
Code
VAD()
VADVREF()
---------------------------------
2
SRES HWLA 16 SRES–()+
×=