Datasheet

611
32133D–11/2011
UC3D
logic waits during this time and then starts the conversion of the enabled channels. When con-
versions of all enabled channels are complete, the ADC is deactivated until the next trigger
event.
Before entering power reduction mode the user must make sure the ADCIFD is idle and that the
Analog-to-Digital Converter cell is inactive. To deactivate the Analog-to-Digital Converter cell the
PRM bit in the ADC Configuration Register (CFG) must be written to one and the ADCIFD must
be idle. To make sure the ADCIFD is idle, write a zero to the Trigger Selection (TRGSEL) field in
the Sequencer Configuration Register (SEQCFG) and wait for the sequencer busy (SBUSY) bit
in the Status Register (SR) to be set. Note that by deactivating the Analog-to-Digital Converter
cell, a startup time penalty as defined in the STARTUP field in the timing register (TIM) will apply
on the next conversion.
28.6.7 Power-up and Startup time
The Analog-to-Digital Converter cell has a minimal startup time when the cell is activated. This
startup time is given in the Electrical Characteristics chapter and must be written to the
STARTUP field in the ADC timing register (TIM) to get correct conversion results. The
TIM.STARTUP field expects the startup time to be represented as the number of GCLK cycles
between 8 and 256 and in steps of 8 that is needed to cover the ADC startup time as specified in
the Electrical Characteristics chapter. The Analog-to-Digital Converter cell is activated at the first
conversion after reset and remains active if CFG.PRM is zero. If CFG.PRM is one, the Analog-
to-Digital Converter cell is automatically deactivated when idle and thus each conversion
sequence will have a initial startup time delay.
28.6.8 Operation Start/Stop
To reset ADCIFD to its initial state, user can enable the ADCIFD after it was previously disabled
thanks to the Enable bit EN in the Control register (CR.EN). Another way to reset ADCIFD is to
write a one in the SWRST field of the Control Register (CR.SWRST). In both cases configuration
registers won’t be affected.
28.6.9 Sample and hold time
A minimal Sample and Hold Time is necessary for the ADCIFD to guarantee the best converted
final value when switching between ADC channels. This time depends on the input impedance
of the analog input, but also on the output impedance of the driver providing the signal to the
analog input, as there is no input buffer amplifier. The Sample and Hold time by default is one
GCLK period and can be increased by programming the SHTIM field in the ADC timing register
(TIM). A null value means that no additional GCLK period are waited to charge the input sam-
pling capacitor, the maximum achievable additional GCLK period number is 15.
28.6.10 Analog reference
Please refer to the Electrical Characteristics chapter.
Please, note that it is recommended to insert a decoupling capacitor between ADVREF and
GNDANA externally to achieve maximum precision.
28.6.11 Conversion range and sampling rates
The conversion voltage amplitude range is [0, ADVREF].