Datasheet

610
32133D–11/2011
UC3D
28.6.4 ADC Sequencer operating modes
28.6.4.1 General
The ADC sequencer consists in a mult-conversion sequencer. A sequence consists in a set of
conversions to perform successively. The maximum number of conversions is 16, the actual
number of conversions is given by the CNVNB field in the SEQCFG register
(SEQCFG.CNVNB). After a conversion, the digital value of the selected channel is stored in the
Last Converted Value register (LCV). It is also possible to sample the same channel multiple
times, allowing the user to perform "oversampling", which gives increased resolution over tradi-
tional single-sampled conversion results.
28.6.4.2 Sequencer Behavior on a STRIG event
Thanks to the STRIGB field in the Sequencer Configuration Register (SEQCFG), two different
behaviors are possible:
•
0: All sequence conversions are performed on a STRIG event
• 1: The sequencer runs across the sequence conversion per conversion
28.6.4.3 Sequencer start/stop mode
Thanks to the SA bit in the SEQCFG register (SEQCFG.SA), the behavior of the sequencer at
the end of a sequence can be changed.
•
0: The sequencer waits for software acknowledge (acknowledge is done by writing a 1 in the SEOS bit of
the SCR register (SEQCFG.SEOS)).
• 1: The sequencer will restart automatically a new sequence on a new STRIG event. Results will be
overwritten if not processed.
The LOVR bit in SR register (SR.LOVR) indicates that an overrun error occurred. This means
that the LCV register is updated with a new conversion result but previous one has not been
read . Events such as end-of-sequence or end-of-conversion can be catched by interrupt servic-
ing or polling routines thanks to the SEOS and SEOC bits in the SR register (SR.SEOS and
SR.SEOC).
28.6.5 ADC clock configuration
The ADC analog cell clock frequency (GCLK) should be programmed to provide an ADC clock
frequency accordingly to the maximum sampling rate parameter given in the Electrical Charac-
teristics section. Failing to do so may result in incorrect Analog-to-Digital Converter operation.
The ADC cell converts an input voltage in 10 GCLK periods and takes at least SHTIM+1 GCLK
periods to sample.
Thus, the maximum achievable ADC sampling frequency is:
28.6.6 Power Reduction Mode
The Power Reduction Mode maximizes power saving by automatically deactivating the Analog-
to-Digital Converter cell when it is not being used for conversions. The Power Reduction Mode is
enabled by writing a one to the Power Reduction Mode (PRM) bit in the Configuration register
(CFG.PRM). When a trigger occurs while the Power Reduction Mode is enabled, the Analog-to-
Digital Converter cell is automatically activated. As the analog cell requires a startup time, the
FGCLK()
10 SHTIM 1+()+
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