Datasheet

609
32133D–11/2011
UC3D
to be set. If the power reduction mode is on, only SR.EN can tell if the ADCIFD is ready for oper-
ation since startup-time will be performed only when a sequencer trigger event occurs. Please
note that all ADCIFD controls will be ignored until SR.EN goes to ‘1’.
Before the ADCIFD can be used, the I/O Controller must be configured correctly and the Refer-
ence Voltage (ADVREF) signal must be connected. Refer to I/O Controller section for details.
Note that once configured, ADCIFD configuration registers should not be written during opera-
tion since they are permanently used by the ADCIFD. The user must ensure that ADCIFD is
stopped during configuration unless he knows what he is doing.
28.6.2 Basic Operation
To convert analog values to digital values the user must first initialize the ADCIFD as described
in Section 28.6.1. When the ADCIFD is initialized the sequencer must be configured by writing
the Number of Conversions in the Sequence (CNVNB) in the Sequencer Configuration Register
(SEQCFG) and by writing the index channels in the Channel Selection Per Low/High conversion
registers, respectively CSPLC and CSPHC. Configuring channel N for a given conversion
instructs the ADCIFD to convert the analog voltage applied to AD pin N. To start converting data
the user can either manually start a conversion sequence by write a one to the sequencer trigger
event (STRIG) bit in the Control Register (CR) or configure an automatic trigger to initiate the
conversions. The automatic trigger can be configured to trig on many different conditions. Refer
to Section 28.6.13 for details. The result of the conversions are stored in the Last Converted
Value register (LCV) as they become available, overwriting the result from the previous conver-
sion. To avoid data loss if more than one channel is enabled, the user must read the conversion
results as they become available either by using an interrupt handler or by using a Peripheral
DMA channel to copy the results to memory. Failing to do so will result in an Overrun Error con-
dition, indicated by the LOVR bit in the Status Register (SR). To use an interrupt handler the
user must enable the End Of Conversion (EOC) interrupt request by writing a one to the corre-
sponding bit in the Interrupt Enable Register (IER). To clear the interrupt after the conversion
result is read, the user must write a one to the corresponding bit in the Status Clear Register
(SCR). To use a Peripheral DMA Controller channel the user must configure the Peripheral DMA
Controller appropriately. The DMA Controller will, when configured, automatically read con-
verted data as they become available. There is no need to manually clear any bits in the
Interrupt Status Register as this is performed by the hardware. If an Overrun Error condition hap-
pens during DMA operation, the LOVR bit in the SR will be set.
28.6.3 ADC resolution
The ADC supports 8-bit and 10-bit resolution. Resolution can be changed by writing the resolu-
tion field (RS) in the Sequencer Configuration register (SEQCFG). By default, after a reset, the
resolution is set to 10-bit. Note that an external decoupling capacitor connected to ADVREF and
GNDANA is mandatory to achieve maximum resolution.