Datasheet

608
32133D–11/2011
UC3D
28.5 Product dependencies
28.5.1 I/O Lines
The pins used for interfacing the ADCIFD may be multiplexed with I/O Controller lines. The pro-
grammer must first program the I/O controller to assign the desired ADCIFD pins to their
peripheral function. If I/O lines of the ADCIFD are not used by the application, they can be used
for other purposes by the I/O controller.
Not all ADCIFD outputs may be enabled. If an application requires only four channels, then only
four ADCIFD lines will be assigned to ADCIFD outputs.
28.5.2 Power management
If the CPU enters a power reduction mode that disables clocks used by the ADCIFD, the
ADCIFD will stop functioning and resume operation after the system wakes up from power
reduction mode. Before entering a power reduction mode where the clock to the ADCIFD is
stopped, make sure the Analog-to-Digital Converter cell is put in an inactive state.
28.5.3 Clocks
The clock for the ADCIFD bus interface (CLK_ADCIFD) is generated by the Power Manager.
This clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to
disable the ADCIFD before disabling the clock, to avoid freezing the ADCIFD in an undefined
state. Additionally, the ADCIFD depends on a dedicated Generic Clock (GCLK). The GCLK can
be set to a wide range of frequencies and clock sources, and must be enabled by the System
Control Interface (SCIF) before the ADCIFD can be used.
28.5.4 Interrupt controller
The ADCIFD interrupt line is connected on one of the internal sources of the Interrupt Controller.
Using the ADCIFD requires the Interrupt Controller to be programmed first.
Section 28.6.5).
28.5.5 Debug operation
When an external debugger forces the CPU into debug mode:
• the ADCIFD continues normal operation if the bit related to ADCIFD in PDBG register is ‘0’.
PDC access continues normal operation and may interfere with debug operation.
• the ADCIFD is frozen if the bit related to ADCIFD in PDBG register is ‘1’. When the ADCIFD
is frozen, ADCIFD PB registers can still be accessed. Then, reading registers may modify
status bits such as LOVR like in normal operation. PDC access are pending.
28.6 Functional description
28.6.1 Initializing the ADCIFD
To initialize the module the user first needs to configure the ADCIFD clocks (please refer to Sec-
tion 28.5.3). Then he needs to configure the Power Reduction Mode field (PRM) in the
Configuration Register (CFG) and the STARTUP field in the Timing Configuration Register (TIM)
(Please refer to Section 28.6.7). Then he can write a one to the Enable (EN) bit in the Control
Register (CR). The user must check that ADCIFD has started correctly, firstly by checking that
the Enable bit (EN) located in the Status Register (SR) is set. Secondly, If the Power Reduction
Mode is off, he must wait for the startup-done bit (SUD) also located in the Status Register (SR)