Datasheet

607
32133D–11/2011
UC3D
28.3 Block diagram
Figure 28-1. ADCIFD block diagram
28.4 I/O Lines Description
AD0
AD1
AD2
AD3
ADn
VDDANA
Successive
Approximation
Register
Analog-to-Digital
Converter
Sequencer
ADCIFD
GCLK
ADVREF
GPIO Controller
Analog multiplexer
ADTRG
Trigger
Selection
Internal Trigger
Timer
Interrupt Request
DMA request
Adcifd_pevc_eoc
CLK_ADCIFD
User
Interface
Adcifd_pevc_wm
Table 28-1. I/O Lines decription table
Name Description Type
AD0-AD7 Analog input channels Analog
ADVREF Reference voltage Analog
VDDANA Analog power supply Power
GNDANA Analog ground Power
ADTRG External trigger Digital