Datasheet

606
32133D–11/2011
UC3D
28. ADC Interface (ADCIFD)
Rev. 1.0.0.0
28.1 Feature
• Multi-channel single-ended Analog-to-Digital Converter with up to 10-bit resolution
• Sequencer handling multiple conversions
• Numerous trigger sources
–Software
– Embedded 16-bit timer for periodic trigger
– Continuous trigger
– External trigger, rising, falling or any-edge trigger
– Chip dependent Internal trigger
• Multiple sequencer modes:
– Run the whole sequence on a start-of-conversion
– Run a single conversion on a start-of-conversion
• ADC Power Reduction Mode for low power ADC applications
• Window monitor, with selectable channel
• Programmable ADC startup time
28.2 Overview
The ADC interface (ADCIFD) is based on a Successive Approximation Register (SAR) 10-bit
Analog-to-Digital Converter (ADC). It also integrates an analog multiplexer, making possible the
analog-to-digital conversions of multiple analog lines. The conversions extend from 0V to
ADVREF.
The ADC supports 8-bit and 10-bit resolution mode, and conversion results are reported in a
common register for all channels. Conversions can be started for all enabled channels, either by
a software trigger, by detection of a level change on the external trigger pin (ADTRG), or by an
integrated programmable timer.
The ADCIFD also integrates an ADC Power Reduction Mode and a Window Monitor mode, and
connects with one Peripheral DMA Controller channel. These features reduce both power con-
sumption and processor intervention.