Datasheet

553
32133D–11/2011
UC3D
• CPCSTOP: Counter Clock Stopped with RC Compare
1: Counter clock is stopped when counter reaches RC.
0: Counter clock is not stopped when counter reaches RC.
• BURST: Burst Signal Selection
• CLKI: Clock Invert
1: Counter is incremented on falling edge of the clock.
0: Counter is incremented on rising edge of the clock.
• TCCLKS: Clock Selection
BURST Burst Signal Selection
0 The clock is not gated by an external signal.
1 XC0 is ANDed with the selected clock.
2 XC1 is ANDed with the selected clock.
3 XC2 is ANDed with the selected clock.
TCCLKS Clock Selected
0TIMER_CLOCK1
1TIMER_CLOCK2
2TIMER_CLOCK3
3TIMER_CLOCK4
4TIMER_CLOCK5
5XC0
6XC1
7XC2