Datasheet

527
32133D–11/2011
UC3D
25.8 Module Configuration
The specific configuration for each PWMA instance is listed in the following tables. The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
Table 25-4. PWMA Configuration
Feature PWMA
Number of PWM channels 7
Table 25-5. PWMA Clocks
Clock Name Description
CLK_PWMA Clock for the PWMA bus interface
GCLK_PWMA
PWMA output clock source.
The generic clock used for the PWMA is GCLK4
Table 25-6. Register Reset Values
Register Reset Value
VERSION 0x00000200
PARAMETER 0x0000007