Datasheet

515
32133D–11/2011
UC3D
25.7.4 Interlinked Multiple Value Channel Select
Name:
IMCHSEL
Access Type: Write-only
Offset:0x0C
Reset Value: 0x00000000
•
SELn: Channel Select
The duty cycle of the PWMA channel SELn will be updated with the value stored in the DUTYn register when IMCHSEL is
written. If SELn points to a non-implemented channel, the write will be discarded.
Note: The duty registers will be updated with the value stored in the DUTY3, DUTY2, DUTY1 and DUTY0 registers when the IMCH-
SEL register is written. Synchronization takes place immediately when an IMCHSEL register is written. The duty cycle registers
will, however, not be updated until the synchronization is completed and the timebase counter reaches its top value in order to
avoid glitches. When only 8 bits duty cycle value are considered for updating, the four duty cycle values can be written to the
IMDUTY register once. This is equivalent to writing the 8 bits four duty cycle values to the four DUTY registers one by one while
the upper 4 bits remain unchanged.
31 30 29 28 27 26 25 24
SEL3
23 22 21 20 19 18 17 16
SEL2
15 14 13 12 11 10 9 8
SEL1
76543210
SEL0