Datasheet

514
32133D–11/2011
UC3D
25.7.3 Interlinked Multiple Value Duty Register
Name:
IMDUTY
Access Type: Write-only
Offset:0x08
Reset Value: 0x00000000
•
DUTYn: Duty Cycle
The value written to DUTY field n will be automatically written to the least significant 8 bits of the DUTYn register for a PWMA
channel while the most significant 4bits of the DUTYn register are unchanged. Which channel is selected for updating is defined
by the corresponding SEL field in the IMCHSEL register.
To write mulitple channels at a time with more than 8 bits of the duty cycle value, refer to DUTY3/2/1/0 registers.
If the value zero is written to DUTY all affected channels will be disabled. In this state the output waveform will be zero all the
time.
31 30 29 28 27 26 25 24
DUTY3
23 22 21 20 19 18 17 16
DUTY2
15 14 13 12 11 10 9 8
DUTY1
76543210
DUTY0