Datasheet

505
32133D–11/2011
UC3D
25.3 Block Diagram
Figure 25-1. PWMA Block Diagram
25.4 I/O Lines Description
Each channel outputs one PWM waveform on one external I/O line.
25.5 Product Dependencies
In order to use this module, other parts of the system must be configured correctly, as described
below.
PWM Blocks
Channel m
Channel 1
Channel 0
Duty Cycle
Register
COMP
PWMA[m:0]
Interrupt
Handling
IRQ
PB
TOP
Timebase
Counter
SPREAD
Adjust
TOFL
READY
Channel_0
CLK_PWMA
GCLK Domain
PB Clock Domain
Spread
Spectrum
Counter
Sync
GCLK
ETV
Control
Duty Cycle
Channel
Select
WAVEXOR
CWG
CHERR
TCLR
Table 25-1. I/O Line Description
Pin Name Pin Description Type
PWMA[n] Output PWM waveform for one channel n Output