Datasheet

5
32133D–11/2011
UC3D
2. Overview
2.1 Block Diagram
Figure 2-1. Block Diagram
SYSTEM CONTROL
INTERFACE
INTERRUPT
CONTROLLER
ASYNCHRONOUS
TIMER
PERIPHERAL
DMA
CONTROLLER
HSB-PB
BRIDGE B
HSB-PB
BRIDGE A
S
MM M
S
S
M
EXTERNAL INTERRUPT
CONTROLLER
HIGH SPEED
BUS MATRIX
GENERALPURPOSE I/Os
GENERAL PURPOSE I/Os
PA
PB
EXTINT[8..1]
NMI
G
C
L
K
[
2
.
.
0
]
PA
PB
SPI
DMA
MISO, MOSI
NPCS[3..0]
USART0
USART1
USART2
DMA
RXD
TXD
CLK
RTS, CTS
WATCHDOG
TIMER
SCK
JTAG
INTERFACE
TDO
TDI
TMS
CONFIGURATION REGISTERS BUS
64/128KB
FLASH
S
FLASH
CONTROLLER
UC CPU
NEXUS
CLASS 2+
OCD
INSTR
INTERFACE
DATA
INTERFACE
MEMORY INTERFACE
LOCAL BUS
16KB SRAM
LOCAL BUS
INTERFACE
FREQUENCY METER
PWM CONTROLLER
PWM[6..0]
TWI MASTER
DMA
TWI SLAVE
DMA
8-CHANNEL ADC
INTERFACE
DMA
AD[7..0]
ADVREF
POWER MANAGER
RESET
CONTROLLER
SLEEP
CONTROLLER
CLOCK
CONTROLLER
XIN32
XOUT32
OSC32K
RCSYS
XIN0
XOUT0
OSC0
PLL0
BOD
TCK
aWire
R
E
S
E
T
_
N
TWCK
TWD
TWCK
TWD
RC120M
PLL1
USB FS
CONTROLLER
M
INTER-IC SOUND
CONTROLLER
DMA
DOUT
DIN
FSYNC
CLK
MCLK
DP
DM
VBUS
CAPACITIVE TOUCH
SENSOR
CONTROLLER
CSB[24..0]
CSA[24..0]
GLUE LOGIC
CONTROLLER
IN[15..0]
OUT[3:0]
TIMER/COUNTER
A[2..0]
B
[
2
.
.
0
]
CLK[2..0]
DMA
DATAOUT