Datasheet

481
32133D–11/2011
UC3D
ished, and the TWIS will wait for a STOP or REPEATED START. If an ACK bit is
received, the SR.NAK bit remains LOW. The ACK indicates that more data should be
transmitted, jump to step 2. At the end of the ACK/NAK clock cycle, the Byte Transfer
Finished (SR.BTF) bit is set. Note that this is done two CLK_TWIS cycles after TWCK
has been sampled by the TWIS to be LOW (see Figure 24-9). Also note that in the
event that SR.NAK bit is set, it must not be cleared before the SR.BTF bit is set to
ensure correct TWIS behavior.
6. If STOP is received, SR.TCOMP and SR.STO will be set.
7. If REPEATED START is received, SR.REP will be set.
The TWI transfers require the receiver to acknowledge each received data byte. During the
acknowledge clock pulse (9th pulse), the slave releases the data line (HIGH), enabling the mas-
ter to pull it down in order to generate the acknowledge. The slave polls the data line during this
clock pulse and sets the NAK bit in SR if the master does not acknowledge the data byte. A NAK
means that the master does not wish to receive additional data bytes. As with the other status
bits, an interrupt can be generated if enabled in the Interrupt Enable Register (IER).
SR.TXRDY is used as Transmit Ready for the Peripheral DMA Controller transmit channel.
The end of the complete transfer is marked by the SR.TCOMP bit changing from zero to one.
See Figure 24-7 and Figure 24-8.
Figure 24-7. Slave Transmitter with One Data Byte
Figure 24-8. Slave Transmitter with Multiple Data Bytes
TCOMP
TXRDY
Write THR (DATA)
STOP sent by master
TWD
ADATANSDADRR P
NBYTES set to 1
ADATA nASDADRR DATA n+5A PDATA n+m N
TCO M P
TXRDY
Write THR (Data n)
NBYTES set to m
STOP sent by master
TWD
Write THR (Data n+1) Write THR (Data n+m)
Last data sent