Datasheet

477
32133D–11/2011
UC3D
24.7.3 Clocks
The clock for the TWIS bus interface (CLK_TWIS) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the TWIS before disabling the clock, to avoid freezing the TWIS in an undefined state.
24.7.4 DMA
The TWIS DMA handshake interface is connected to the Peripheral DMA Controller. Using the
TWIS DMA functionality requires the Peripheral DMA Controller to be programmed after setting
up the TWIS.
24.7.5 Interrupts
The TWIS interrupt request lines are connected to the interrupt controller. Using the TWIS inter-
rupts requires the interrupt controller to be programmed first.
24.7.6 Debug Operation
When an external debugger forces the CPU into debug mode, the TWIS continues normal oper-
ation. If the TWIS is configured in a way that requires it to be periodically serviced by the CPU
through interrupts or similar, improper operation or data loss may result during debugging.
24.8 Functional Description
24.8.1 Transfer Format
The data put on the TWD line must be 8 bits long. Data is transferred MSB first; each byte must
be followed by an acknowledgement. The number of bytes per transfer is unlimited (see Figure
24-4 on page 477).
Each transfer begins with a START condition and terminates with a STOP condition (see Figure
24-3).
• A high-to-low transition on the TWD line while TWCK is high defines the START condition.
• A low-to-high transition on the TWD line while TWCK is high defines a STOP condition.
Figure 24-3. START and STOP Conditions
Figure 24-4. Transfer Format
TWD
TWCK
Start Stop
TWD
TWCK
Start Address R/W Ack Data Ack Data Ack Stop