Datasheet

405
32133D–11/2011
UC3D
• BITS: Bits Per Transfer
The BITS field determines the number of data bits transferred. Reserved values should not be used.
• CSAAT: Chip Select Active After Transfer
1: The Peripheral Chip Select does not rise after the last transfer is achieved. It remains active until a new transfer is requested
on a different chip select.
0: The Peripheral Chip Select Line rises as soon as the last transfer is achieved.
• CSNAAT: Chip Select Not Active After Transfer (Ignored if CSAAT = 1)
0: The Peripheral Chip Select does not rise between two transfers if the TDR is reloaded before the end of the first transfer and
if the two transfers occur on the same Chip Select.
1: The Peripheral Chip Select rises systematically between each transfer performed on the same slave for a minimal duration
of:
(if DLYBCT field is different from 0)
(if DLYBCT field equals 0)
• NCPHA: Clock Phase
1: Data is captured after the leading (inactive-to-active) edge of SPCK and changed on the trailing (active-to-inactive) edge of
SPCK.
0: Data is changed on the leading (inactive-to-active) edge of SPCK and captured after the trailing (active-to-inactive) edge of
SPCK.
NCPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. NCPHA is used
with CPOL to produce the required clock/data relationship between master and slave devices.
• CPOL: Clock Polarity
1: The inactive state value of SPCK is logic level one.
0: The inactive state value of SPCK is logic level zero.
BITS Bits Per Transfer
0000 8
0001 9
0010 10
0011 11
0100 12
0101 13
0110 14
0111 15
1000 16
1001 4
1010 5
1011 6
1100 7
1101 Reserved
1110 Reserved
1111 Reserved
DLYBCS
CLKSPI
-----------------------
DLYBCS 1+
CLKSPI
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