Datasheet

380
32133D–11/2011
UC3D
Figure 21-5 on page 380shows a block diagram of the SPI when operating in master mode. Fig-
ure 21-6 on page 381 shows a flow chart describing how transfers are handled.
21.7.3.1 Master mode block diagram
Figure 21-5. Master Mode Block Diagram
Baud Rate Generator
RXFIFOEN
4 – Character FIFO
Shift Register
TDRE
RXFIFOEN
4 – Character FIFO
PS
PCSDEC
Current
Peripheral
MODF
MODFDIS
MSTR
SCBR
CSR0..3
CSR0..3
CPOL
NCPHA
BITS
RDR
RD
RDRF
OVRES
TD
TDR
RDR
CSAAT
CSNAAT
CSR0..3
PCS
MR
PCS
TDR
SPCK
CLK_SPI
MISO MOSI
MSBLSB
NPCS1
NPCS2
NPCS3
NPCS0
SPI
Clock
0
1
0
1
0
1
NPCS0