Datasheet

374
32133D–11/2011
UC3D
20.8 Module Configuration
The specific configuration for each USART instance is listed in the following tables.The module
bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-
ager chapter for details.
20.8.1 Clock Connections
Each USART can be connected to an internally divided clock:
20.8.2 Register Reset Values
Table 20-16.
Module Configuration
Feature USART0 USART1 USART2
SPI Logic Implemented Implemented Implemented
LIN Logic Not Implemented Not Implemented Not Implemented
RS485 Logic Not Implemented Not Implemented Not Implemented
Manchester Logic Not Implemented Not Implemented Not Implemented
Modem Logic Not Implemented Not Implemented Not Implemented
IRDA Logic Not Implemented Not Implemented Not Implemented
Fractional Baudrate Not Implemented Not Implemented Not Implemented
ISO7816 Not Implemented Not Implemented Not Implemented
DIV 8 8 8
Receiver Time-out Counter Size
(Size of the RTOR.TO field)
8-bits 8-bits 8-bits
Table 20-17. Module Clock Name
Module Name Clock Name
USART0 CLK_USART0
USART1 CLK_USART1
USART2 CLK_USART2
Table 20-18. USART Clock Connections
USART Source Name Connection
0
Internal CLK_DIV PBA Clock / 8
1
2
Table 20-19.
Register Reset Value
VERSION 0x00000440