Datasheet

363
32133D–11/2011
UC3D
20.7.5 Interrupt Mask Register
Name:
IMR
Access Type: Read-only
Offset: 0x10
Reset Value: 0x00000000
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
A bit in this register is cleared when the corresponding bit in IDR is written to one.
A bit in this register is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––CTSIC– – –
15 14 13 12 11 10 9 8
– – NACK RXBUFF – ITER/UNRE TXEMPTY TIMEOUT
76543210
PARE FRAME OVRE – – RXBRK TXRDY RXRDY