Datasheet

36
32133D–11/2011
UC3D
7. Boot Sequence
This chapter summarizes the boot sequence of the UC3D. The behavior after power-up is con-
trolled by the Power Manager. For specific details, refer to the Power Manager chapter.
7.1 Starting of Clocks
After power-up, the device will be held in a reset state by the Power-On Reset circuitry for a
short time to allow the power to stabilize throughout the device. After reset, the device will use
the System RC Oscillator (RCSYS) as clock source.
On system start-up, all clocks to all modules are running. No clocks have a divided frequency; all
parts of the system receive a clock with the same frequency as the System RC Oscillator.
7.2 Fetching of Initial Instructions
After reset has been released, the AVR32UC CPU starts fetching instructions from the reset
address, which is 0x80000000. This address points to the first address in the internal Flash.
The code read from the internal Flash is free to configure the system to divide the frequency of
the clock routed to some of the peripherals, and to gate the clocks to unused peripherals.