Datasheet

356
32133D–11/2011
UC3D
20.7.1 Control Register
Name:
CR
Access Type: Write-only
Offset: 0x0
Reset Value: 0x00000000
• RTSDIS/RCS: Request to Send Disable/Release SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS pin high.
Writing a one to this bit when USART is in SPI master mode releases NSS (RTS pin).
• RTSEN/FCS: Request to Send Enable/Force SPI Chip Select
Writing a zero to this bit has no effect.
Writing a one to this bit when USART is not in SPI master mode drives RTS low.
Writing a one to this bit when USART is in SPI master mode when;
FCS=0: has no effect.
FCS=1: forces NSS (RTS pin) low, even if USART is not transmitting, in order to address SPI slave devices supporting the
CSAAT Mode (Chip Select Active After Transfer).
• RETTO: Rearm Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit reloads the time-out counter and clears CSR.TIMEOUT.
• RSTNACK: Reset Non Acknowledge
Writing a zero to this bit has no effect.
Writing a one to this bit clears CSR.NACK.
• SENDA: Send Address
Writing a zero to this bit has no effect.
Writing a one to this bit will in multidrop mode send the next character written to THR as an address.
• STTTO: Start Time-out
Writing a zero to this bit has no effect.
Writing a one to this bit will abort any current time-out count down, and trigger a new count down when the next character has
been received. CSR.TIMEOUT is also cleared.
• STPBRK: Stop Break
Writing a zero to this bit has no effect.
Writing a one to this bit will stop the generation of break signal characters, and then send ones for TTGR.TG duration, or at least
12 bit periods. No effect if no break is being transmitted.
31 30 29 28 27 26 25 24
––––––––
23 22 21 20 19 18 17 16
––––RTSDIS/RCSRTSEN/FCS––
15 14 13 12 11 10 9 8
RETTO RSTNACK – SENDA STTTO STPBRK STTBRK RSTSTA
76543210
TXDIS TXEN RXDIS RXEN RSTTX RSTRX – –