Datasheet
339
32133D–11/2011
UC3D
20.4 I/O Lines Description
20.5 Product Dependencies
20.5.1 I/O Lines
The USART pins may be multiplexed with the I/O Controller lines. The user must first configure
the I/O Controller to assign these pins to their peripheral functions. Unused I/O lines may be
used for other purposes.
To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up
is required. If the hardware handshaking feature or modem mode is used, the internal pull up on
TXD must also be enabled.
20.5.2 Clocks
The clock for the USART bus interface (CLK_USART) is generated by the Power Manager. This
clock is enabled at reset, and can be disabled in the Power Manager. It is recommended to dis-
able the USART before disabling the clock, to avoid freezing the USART in an undefined state.
20.5.3 Interrupts
The USART interrupt request line is connected to the interrupt controller. Using the USART
interrupt requires the interrupt controller to be programmed first.
Table 20-2. I/O Lines Description
Name Description Type Active Level
CLK Serial Clock I/O
TXD
Transmit Serial Data
or Master Out Slave In (MOSI) in SPI master mode
or Master In Slave Out (MISO) in SPI slave mode
Output
RXD
Receive Serial Data
or Master In Slave Out (MISO) in SPI master mode
or Master Out Slave In (MOSI) in SPI slave mode
Input
CTS
Clear to Send
or Slave Select (NSS) in SPI slave mode
Input Low
RTS
Request to Send
or Slave Select (NSS) in SPI master mode
Output Low