Datasheet

338
32133D–11/2011
UC3D
20.3 Block Diagram
Figure 20-1. USART Block Diagram
Peripheral DMA
Controller
Channel Channel
Interrupt
Controller
Power
Manager
DIV
Receiver
Transmitter
User
Interface
I/O
Controller
RXD
RTS
TXD
CTS
CLK
BaudRate
Generator
USART
Interrupt
CLK_USART
CLK_USART/DIV
USART
Peripheral bus
Table 20-1. SPI Operating Mode
PIN USART SPI Slave SPI Master
RXD RXD MOSI MISO
TXD TXD MISO MOSI
RTS RTS – CS
CTS CTS CS –