Datasheet

33
32133D–11/2011
UC3D
6. Memories
6.1 Embedded Memories
• Internal High-Speed Flash
– 128Kbytes (ATUC128D)
– 64Kbytes (ATUC64D)
• 0 Wait State Access at up to 24 MHz in Worst Case Conditions
• 1 Wait State Access at up to 48 MHz in Worst Case Conditions
• Pipelined Flash Architecture, allowing burst reads from sequential Flash locations,
hiding penalty of 1 wait state access
• 100 000 Write Cycles, 15-year Data Retention Capability
• 4ms Page Programming Time, 8 ms Chip Erase Time
• Sector Lock Capabilities, Bootloader Protection, Security Bit
• 32 Fuses, Erased During Chip Erase
• User Page For Data To Be Preserved During Chip Erase
• Internal High-Speed SRAM, Single-cycle access at full speed
–16Kbytes
6.2 Physical Memory Map
The system bus is implemented as a bus matrix. All system bus addresses are fixed, and they
are never remapped in any way, not even in boot. Note that AVR32UC CPU uses unsegmented
translation, as described in the AVR32 Architecture Manual. The 32-bit physical address space
is mapped as follows:
Table 6-1. UC3D Physical Memory Map
6.3 Peripheral Address Map
Device Embedded SRAM Embedded Flash HSB-PB Bridge A HSB-PB Bridge B
Start Address 0x0000_0000 0x8000_0000 0xFFFF_0000 0xFFFE_0000
Size
ATUC128D
16 Kbytes 128 Kbytes 64 Kbytes 64 Kbytes
ATUC64D
16 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes
Table 6-2. Peripheral Address Mapping
Address Peripheral Name
0xFFFE0000
USBC USB 2.0 Interface - USBC
0xFFFE1000
HMATRIX HSB Matrix - HMATRIX
0xFFFE1400
FLASHCDW Flash Controller - FLASHCDW
0xFFFF0000
PDCA Peripheral DMA Controller - PDCA
0xFFFF1000
INTC Interrupt controller - INTC