Datasheet

327
32133D–11/2011
UC3D
19.7.2.11 Endpoint n Status Register
Register Name: UESTAn, n in [0..6]
Access Type: Read-Only 0x0100
Offset: 0x0130 + (n * 0x04)
Reset Value: 0x00000000
• CTRLDIR: Control Direction
Writing a zero or a one to this bit has no effect.
This bit is cleared after a SETUP packet to indicate that the following packet is an OUT packet.
This bit is set after a SETUP packet to indicate that the following packet is an IN packet.
• CURRBK: Current Bank
This bit is set for non-control endpoints, indicating the current bank:
This field may be updated one clock cycle after the RWALL bit changes, so the user should not poll this field as an interrupt bit.
• NBUSYBK: Number of Busy Banks
This field is set to indicate the number of busy banks:
31 30 29 28 27 26 25 24
--------
23 22 21 20 19 18 17 16
- - - - - - CTRLDIR -
15 14 13 12 11 10 9 8
CURRBK NBUSYBK RAMACERI
-
DTSEQ
76543210
-
STALLEDI/
CRCERRI
- NAKINI NAKOUTI
RXSTPI/
ERRORFI
RXOUTI TXINI
CURRBK Current Bank
00Bank0
01Bank1
10Reserved
11Reserved
NBUSYBK Number of Busy Banks
0 0 0 (all banks free)
011
102
11Reserved