Datasheet

321

32133D–11/2011

UC3D

19.7.2.6 Device Global Interrupt Enable Clear Register

Access Type: Write-Only

Offset: 0x0014

Reset Value: 0x00000000

Note: 1. EPnINTEC bits are within the range from EP0INTEC to EP6INTEC.

Writing a zero to a bit in this register has no effect.

Writing a one to a bit in this register will clear the corresponding bit in UDINTE.

These bits always read as zero.

31 30 29 28 27 26 25 24

--------

23 22 21 20 19 18 17 16

- - - EP8INTEC

(1)

EP7INTEC

(1)

EP6INTEC

(1)

EP5INTEC

(1)

EP4INTEC

(1)

15 14 13 12 11 10 9 8

EP3INTEC

(1)

EP2INTEC

(1)

EP1INTEC

(1)

EP0INTEC - - - -

76543210

- UPRSMEC EORSMEC WAKEUPEC EORSTEC SOFEC - SUSPEC