Datasheet

263
32133D–11/2011
UC3D
Note: 1. The reset values for these registers are device specific. Please refer to the Module Configuration section at the end of this
chapter.
0x0C0 Glitch Filter Enable Register Read/Write GFER Read/Write -
(1)
NN
0x0C4 Glitch Filter Enable Register Set GFERS Write-only N N
0x0C8 Glitch Filter Enable Register Clear GFERC Write-only N N
0x0CC Glitch Filter Enable Register Toggle GFERT Write-only N N
0x0D0 Interrupt Flag Register Read IFR Read-only -
(1)
N N
0x0D4 Interrupt Flag Register - - - N N
0x0D8 Interrupt Flag Register Clear IFRC Write-only N N
0x0DC Interrupt Flag Register - - - N N
0x1A0 Lock Register Read/Write LOCK Read/Write -
(1)
N Y
0x1A4 Lock Register Set LOCKS Write-only N N
0x1A8 Lock Register Clear LOCKC Write-only N Y
0x1AC Lock Register To g gl e LOCKT Write-only N Y
0x1E0 Unlock Register Read/Write UNLOCK Write-only N N
0x1E4 Access Status Register Read/Write ASR Read/Write N
0x1F8 Parameter Register Read PARAMETER Read-only -
(1)
N N
0x1FC Version Register Read VERSION Read-only -
(1)
N N
Table 18-2. GPIO Register Memory Map
Offset Register Function Register Name Access Reset
Config.
Protection
Access
Protection