Datasheet

261
32133D–11/2011
UC3D
ten to one. Again all bits written to zero remain unchanged. Note that for some registers (e.g.
IFR), not all access methods are permitted.
Note that for ports with less than 32 bits, the corresponding control registers will have unused
bits. This is also the case for features that are not implemented for a specific pin. Writing to an
unused bit will have no effect. Reading unused bits will always return 0.
18.7.2 Configuration Protection
In order to protect the configuration of individual GPIO pins from software failure, configuration
bits for individual GPIO pins may be locked by writing a one to the corresponding bit in the LOCK
register. While this bit is one, any write to the same bit position in any lockable GPIO register
using the Peripheral Bus (PB) will not have an effect. The CPU Local Bus is not checked and
thus allowed to write to all bits in a CPU Local Bus mapped register no mather the LOCK value.
The registers required to clear bits in the LOCK register are protected by the access protection
mechanism described in Section 18.7.3, ensuring the LOCK mechanism itself is robust against
software failure.
18.7.3 Access Protection
In order to protect critical registers from software failure, some registers are protected by a key
protection mechanism. These registers can only be changed by first writing the UNLOCK regis-
ter, then the protected register. Protected registers are indicated in Table 18-2. The UNLOCK
register contains a key field which must always be written to 0xAA, and an OFFSET field corre-
sponding to the offset of the register to be modified.
The next write operation resets the UNLOCK register, so if the register is to be modified again,
the UNLOCK register must be written again.
Attempting to write to a protected register without first writing the UNLOCK register results in the
write operation being discarded, and the Access Error bit in the Access Status Register
(ASR.AE) will be set.
Table 18-2. GPIO Register Memory Map
Offset Register Function Register Name Access Reset
Config.
Protection
Access
Protection
0x000 GPIO Enable Register Read/Write GPER Read/Write -
(1)
YN
0x004 GPIO Enable Register Set GPERS Write-only Y N
0x008 GPIO Enable Register Clear GPERC Write-only Y N
0x00C GPIO Enable Register Toggle GPERT Write-only Y N
0x010 Peripheral Mux Register 0 Read/Write PMR0 Read/Write -
(1)
Y N
0x014 Peripheral Mux Register 0 Set PMR0S Write-only Y N
0x018 Peripheral Mux Register 0 Clear PMR0C Write-only Y N
0x01C Peripheral Mux Register 0 Tog gl e PMR0T Write-only Y N
0x020 Peripheral Mux Register 1 Read/Write PMR1 Read/Write -
(1)
YN
0x024 Peripheral Mux Register 1 Set PMR1S Write-only Y N
0x028 Peripheral Mux Register 1 Clear PMR1C Write-only Y N