Datasheet

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32133D–11/2011
UC3D
Figure 18-5. Interrupt Timing with Glitch Filter Enabled
18.6.2.7 CPU Local Bus
The CPU Local Bus can be used for application where low latency read and write access to the
Output Value Register (OVR) and Output Drive Enable Register (ODER) is required. The CPU
Local Bus allows the CPU to configure the mentioned GPIO registers directly, bypassing the
shared Peripheral Bus (PB).
To avoid data loss when using the CPU Local Bus, the CLK_GPIO must run at the same fre-
quency as the CLK_CPU. See Section 18.5.2 for details.
The CPU Local Bus is mapped to a different base address than the GPIO but the OVER and
ODER offsets are the same. See the CPU Local Bus Mapping section in the Memories chapter
for details.
CLK_GPIO
Pin Level
IFR