Datasheet

252

32133D–11/2011

UC3D

17.7 Module Configuration

The specific configuration for each FREQM instance is listed in the following tables. The module

bus clocks listed here are connected to the system bus clocks. Please refer to the Power Man-

ager chapter for details.

Table 17-2. Module Clock Name

Module Name Clock Name Description

FREQM

CLK_FREQM Bus interface clock

CLK_MSR Measured clock

CLK_REF Reference clock

Table 17-3. Register Reset Values

VERSION 0x00000310

Table 17-4. Clock Sources for CLK_MSR

CLKSEL Clock/Oscillator Description

0 CLK_CPU The clock the CPU runs on

1 CLK_HSB High Speed Bus clock

2 CLK_PBA Peripheral Bus A clock

3 CLK_PBB Peripheral Bus B clock

4 OSC0 Output clock from Oscillator 0

5 OSC32K Output clock from OSC32K

6 RCSYS Output clock from RCSYS Oscillator

7 PLL0 Output clock from PLL0

8 PLL1 Output clock from PLL1

10-18 GCLK0-8 Generic clocks

19 RC120M AW clock Output clock from RC120M to AW

20-31 Reserved

Table 17-5. Clock Sources for CLK_REF

REFSEL Clock/Oscillator Description

0 RCSYS System RC oscillator clock

1 OSC32K Output clock from OSC32K

2 OSC0 Output clock from Oscillator O

3 GCLK0 Generic Clock 0

4-7 Reserved