Datasheet

224
32133D–11/2011
UC3D
16.7.3 Interrupt Mask Register
Name: IMR
Access Type: Read-only
Offset: 0x008
Reset Value: 0x00000000
•INTn: External Interrupt n
0: The corresponding interrupt is disabled.
1: The corresponding interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
Please refer to the Module Configuration section for the number of external interrupts.
• NMI: Non-Maskable Interrupt
0: The Non-Maskable Interrupt is disabled.
1: The Non-Maskable Interrupt is enabled.
This bit is cleared when the corresponding bit in IDR is written to one.
This bit is set when the corresponding bit in IER is written to one.
31 30 29 28 27 26 25 24
- INT30 INT29 INT28 INT27 INT26 INT25 INT24
23 22 21 20 19 18 17 16
INT23 INT22 INT21 INT20 INT19 INT18 INT17 INT16
15 14 13 12 11 10 9 8
INT15 INT14 INT13 INT12 INT11 INT10 INT9 INT8
76543210
INT7 INT6 INT5 INT4 INT3 INT2 INT1 NMI